Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device

The above object and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram a conventional data input circuit for use in a semiconductor device;

FIG. 2 is a circuit diagram of a data input circuit according to an exemplary embodiment of the present invention;

FIG. 3 is a circuit diagram of a data input circuit according to another exemplary embodiment of the present invention;

FIG. 4 is a circuit diagram of a data input circuit according to another exemplary embodiment of the present invention;

FIG. 5 is a circuit diagram of a data input circuit according to another exemplary embodiment of the present invention;

FIG. 6 is a circuit diagram of a data input circuit according to another exemplary embodiment of the present invention; and

FIGS. 7 ( a ) and ( b ) are circuit diagrams of a strobe signal inputting buffer and a data input buffer shown in FIG. 6, respectively.

FIG. 2 is a circuit diagram of a data input circuit 200 according to an exemplary embodiment of the present invention. Referring to FIG. 2, the data input circuit 200 includes N latching units 210 _i and a bus 250 , where i is an integer from 1 to N, and N is a natural number greater than 2. For convenience, the N latching units 210 _i will now be described as first through N th latching units 210 _i.

Each of the first through N th latching units 210 _ 1 through 210 _N latches one of N groups of data D<0> through D<N−1> in response to a reference clock SC. In particular, the first latching unit 210 — 1 latches the first group of data D<0>, the second latching unit 210 _ 2 latches the second group of data D<1>, and the remaining latching units 210 _i latch corresponding groups of data, respectively (i is an integer from 3 to N). The reference clock SC may be a signal input via a clock pin (not shown) of a semiconductor device, and may be used as a fetch signal when fetching N groups of data. In an exemplary embodiment, one group of data includes one bit. Thus, the N groups of data D<0> through D<N−1> include N bits.

The bus 250 transmits the reference clock SC and data D<j> input via outer pins of a semiconductor device, and data D<j> to the first through N th latching units 210 _i, respectively, where j is an integer from 0 to N_ 1 and i is an integer from 1 to N.

In an exemplary detailed configuration of the first through N th latching units 210 _i, each of these latching units 210 _i may include a clock buffer 23 i , a data buffer 24 i , N−1 dummy elements Cd and a latch 220 _i.

The clock buffers 23 i buffer the reference clock SC, and the data buffers 24 i buffer a corresponding group of data out of N groups of data D<j> (i is an integer from 1 through N and j is an integer 0 through N−1). That is, the data buffer 241 of the first latching unit 210 _ 1 buffers the first group of data D<0>, and the data buffer 242 of the second latching unit 210 _ 2 buffers the second group of data D<1>. Also, the buffers 24 i of the other latches 210 _i buffer corresponding groups of the data, respectively (i is an integer from 3 to N).

Each dummy element Cd receives the N groups of data, except for a group of data input to the data buffer 24 i of a latching unit 210 _i to which the dummy element Cd belongs. For example, the N−1 dummy elements Cd of the first latching unit 210 _ 1 receive the second through N th groups of data D<j>, respectively (j is an integer from 1 to N−1). The N−1 dummy elements Cd of the second latching unit 210 _ 2 receive the first group of data D<0> and the third through N th groups of data D<j>, respectively (j is an integer from 2 to N−1). Similarly, the dummy elements Cd of the third through N th latching units 210 _i receive corresponding groups of data, respectively (i is an integer from 3 to N).

In an exemplary embodiment, each dummy element Cd is a capacitor having the same or substantially the same capacitance as the clock buffer 23 i (i is an integer from 1 to N).

The latch 220 _i latches data output from the data buffer 24 i in synchronization with a signal output from the clock buffer 23 i (i is an integer from 1 to N). That is, the latch 220 _ 1 of the first latching unit 210 _ 1 latches the first group of data D<0>, and the latch 220 _ 2 of the second latching unit 210 _ 2 latches the second group of data D<1>. Likewise, the latches 220 _i of the other latching units 210 _i latch corresponding groups of data, respectively (i is an integer from 3 to N) as in the data buffers 241 and 242 of the first and second latching units 210 _ 1 and 210 _ 2 .

It is assumed that the clock buffer 23 i and the data buffer 24 i have the same or substantially the same size and/or structure (i is an integer from 1 through N), and each clock buffer 23 i and each data buffer 24 i have the same or substantially the same capacitance. Also, the value of the capacitance of each clock or data buffer 23 i or 24 i is determined as ‘Cin’. In this case, each dummy element Cd has a capacitance Cin, i.e., each dummy element Cd is a capacitor having the capacitance Cin.

The N−1 dummy elements Cd of the first latching unit 210 _ 1 are capacitors formed between a grounding voltage and each bus that transmits the second through N th groups of data D<j> (j is an integer from 1 through N−1), and the N−1 dummy elements Cd of the second latching unit 210 _ 2 are capacitors formed between a grounding voltage and each bus that transmits the first group of data D<0> and the third through N th groups of data D<j> (j is an integer from 2 through N−1). Similarly, the dummy elements Cd of the third through N th latching units 210 —i are capacitors formed between a grounding voltage and each bus that transmits corresponding data (i is an integer from 3 through N). The capacitors which constitute the dummy elements Cd can be variously formed, as would be known to one of ordinary skill in the art.

As described above, a data input circuit according to an exemplary embodiment of the present invention includes the dummy elements Cd whose capacitances are the same or substantially the same as that of the clock buffer 23 i (i is an integer from 1 through N). Therefore, a loading difference between the reference clock SC and each data D<j> can be reduced or minimized (j is an integer from 0 through N−1).

FIG. 3 is a circuit diagram of a data input circuit 300 according to another exemplary embodiment of the present invention. Referring to FIG. 3, as in the data input circuit 200 according to the previous exemplary embodiment, the data input circuit 300 includes first through N th latching units 310 _i and a bus 350 . Here, i is an integer from 1 through N, and N is a natural number greater than 2.

In an exemplary embodiment, each of the first through N th latching units 310 _i includes a clock buffer 33 i , a data buffer 34 i , N−1 dummy elements Bd, and a latch 320 13 i.

The clock buffers 33 i , the data buffers 34 i , the latches 320 _i, which are respectively included in one of the first through N th latches 310 i and the bus 350 , may be the same or substantially the same as the clock buffers 23 i , the data buffers 24 i , and the latching units 220 _ 1 , and the bus 250 which are included in the data input circuit 200 . Thus a detailed description of these elements can be omitted. Here, i is an integer from 1 to N.

Each of the dummy elements Bd receives one of the other groups of data except for the group of data that is input to the data buffer 34 i to which each of the dummy elements Bd belongs (i is an integer from 1 through N). For example, the N−1 dummy elements Bd of the first latching unit 310 _ 1 receive the second through N th groups of data D<j>, respectively (j is an integer from 1 through N−1), and the N−1 dummy elements Bd of the second latching unit 310 _ 2 receive the first group of data D<0> and the third through N th groups of data D<j>, respectively (j is an integer from 2 to N−1). Also, the dummy elements Bd of the third and N th latching units 310 _i receive corresponding group of data, respectively (i is an integer from 3 to N). In an exemplary embodiment, each of the dummy elements Bd is a buffer having the same or substantially the same structure and/or size as the clock buffer 33 i and the data buffers 34 i (i is an integer from 1 through N). However, data output from the dummy buffer Bd is not input to the corresponding latching unit 310 _i.

In an exemplary embodiment, an inverter including at least one pMOS transistor and at least one nMOS transistor can be adopted as a buffer that is used as the dummy elements Bd. The structure of this inverter-type buffer is well known to those skilled in the art and, thus, its detailed description can be omitted here.

Use of the dummy buffers Bd having the same or substantially the same structure and/or size as the clock buffer 33 i and the data buffer 34 i reduces a loading difference between the reference clock SC and each group of data D<j>. Here, i is an integer from 1 through N, and j is an integer from 0 through N−1. A reduced loading difference between the reference clock SC and each group of data D<j> results in a reduction in the occurrence of skew therebetween.

FIG. 4 is a circuit diagram of a data input circuit 400 , according to another exemplary embodiment of the present invention. Referring to FIG. 4, the data input circuit 400 includes first through N th latching units 410 _i and a bus 460 , as in the data input circuit 200 according to the previous exemplary embodiment (i is an integer from 1 through N). Because the second through N th latching units 410 _ 2 through 410 _N have the same structure as the first latching unit 410 _ 1 , only the first latching unit 410 _ 1 is illustrated in FIG. 4 for convenience. Here, N is a natural number greater than 2.

The first latching unit 410 _ 1 includes a clock buffer 431 , a data buffer 441 , N−1 dummy elements 45 i , and a latch 420 _ 1 (i is an integer from 3 through N). Each of the second and N th latching units (not shown) includes a clock buffer, a data buffer, N−1 dummy elements, and a latch.

The bus 460 , the clock buffer 431 , the data buffer 441 , and the latch 420 _ 1 are the same as the bus 250 , the clock buffer 23 i , the data buffer 24 i , and the latch 220 _i that are included in the data input circuit 200 according to the previous exemplary embodiment (i is an integer from 1 through N). Thus a detailed description of these elements can be omitted here.

Each of the dummy elements 45 i receives each group of data D<j>, except for the group of data D<0> input to the data buffer 441 of the latching unit 410 _ 1 to which this dummy element 45 i belongs (i is an integer from 3 through N and j is an integer from 1 through N−1). Although not illustrated in the drawings, the N−1 dummy elements of the second latching unit receive the first group of data D<0> and the third through N th groups of data D<j> (j is an integer from 2 through N−1).

In an exemplary embodiment, each of the dummy elements 45 i (i is an integer from 3 through N) includes an nPMOS transistor PM 1 whose drain and source are connected to a power source voltage VDD and whose gate is connected to the bus 460 that transmits received data, and includes an nMOS transistor NM 1 whose drain and source are connected to grounding voltage and whose gate is connected to the bus 460 that transmits received data.

In the case of the first dummy element 453 of the first latching unit 410 _ 1 , the gates of the pMOS transistor PM 1 and nMOS transistor NM 1 of the first dummy element 453 are connected to the bus 460 that transmits the second group of data D<1>. The gates of the pMOS transistor and nMOS transistor of the second dummy element 454 are connected to the bus 460 that transmits the third group of data D<2>. Likewise, gates of the pMOS transistors and nMOS transistors of the other dummy elements 45 i (i is an integer from 5 through N) are connected to the bus 460 that transmits received data D<j> (j is an integer from 3 through N−1).

In an exemplary embodiment, each dummy element 45 i (i is an integer from 3 through N) has the same or substantially the same capacitance as the clock buffer 431 . Although not shown in the drawings, each of the dummy elements of the second through N th latches (not shown) receives a corresponding group of data except for the group of data input to the data buffer of the latching unit to which the second through N th latches belong. Also, each dummy element has the same or substantially the same capacitance as the clock buffer.

Use of the dummy elements of FIG. 4 reduces loading difference between the reference clock SC and each group of data D<j> (j is an integer from 0 through N−1), and results in less power consumption.

5 is a circuit diagram of a data input circuit 500 according to another exemplary embodiment of the present invention. Referring to FIG. 5, the data input circuit 500 includes eight latching units 510 _i, eight data input buffers 540 _i, a strobe signal input buffer 540 _ 9 , a repeating unit 550 , and a bus 560 . Here, i is an integer from 1 through 8.

The data input circuit 500 according to an exemplary embodiment is similar to the data input circuits 200 through 400 of the previous exemplary embodiments. The data input circuit 500 is different from the data input circuits 100 through 400 in that N, which is illustrated in FIGS. 2 through 4, is fixed as eight, i.e., the numbers of some elements such as latching units and latches are determined to be eight. Also, the eight data input buffers 540 _i, the strobe signal input buffer 540 _ 9 , and the repeater 550 are further included in the data input circuit 500 .

The data input buffers 540 _i (i is an integer from 1 through 8) buffers first through eighth external data DQ 0 through DQ 7 input external to a semiconductor device via a pad (not shown) and outputs the result as first through eighth data D< 0 > through D<N−1>, respectively, which are internal signals. The strobe signal input buffer 540 _ 9 buffers a data strobe signal DQS input externally and outputs it as a reference clock SC which is an internal fetch signal. Otherwise, the strobe signal input buffer 540 _ 9 may buffer the data strobe signal DQS and its inversion signal DQSB so as to generate the reference clock SC.

Inclusion of the data input buffers 540 _i (i is an integer from 1 through 8) and the strobe signal input buffer 540 _ 9 into the data input circuits 200 through 400 is also possible, although not specifically shown in the data input circuits 200 through 400 according to the previous exemplary embodiments.

Each of the eight latching units 510 _i includes a latch 520 _i and a dummy input unit 530 _i (i is an integer from 1 through 8). As like in the latches 220 _ 1 through 220 _N, the latches 520 _i latch a related group of data D<i> in synchronization with the reference clock SC (j is an integer from 0 through 7). In detail, the first latch 520 _ 1 , the second latch 520 _ 2 , . . . , and the eighth latch 520 _ 8 latch first data D<0>, second data D<1>, . . . , eighth data D<7>, respectively.

The dummy input units 530 _i are circuits to which other data, except for data latched by a corresponding latch 520 _i, are input as dummy data, respectively (i is an integer from 1 through 8). The dummy input units 530 _i are circuits corresponding to the N−1 dummy elements according to the first through third embodiment, shown in FIGS. 2 through 4. That is, the first dummy input unit 530 _ 1 receives other data D<j> (j is an integer from 1 through 7) except for the first data D<0> latched by the first latch 520 _ 1 . The second dummy input unit 530 _ 2 receives other data D<j> (j is 0 and an integer from 2 through 7) except for the second data D< 1 > latched by the second latch 520 _ 1 . The dummy input units 530 _i may be any of the dummy devices described above in conjunction with other exemplary embodiments.

The repeating unit 550 is a circuit for amplifying data and the reference clock SC when the length of a bus between the latches 510 _i and the data input buffers 540 _i (i is an integer from 1 through 8) or between the latches 510 _i and the strobe signal input buffer 540 _ 9 is long. The repeating unit 550 includes nine repeaters.

In the data input circuit 500 according to an exemplary embodiment, all data D<j> (j is an integer from 0 through 7) and the reference clock SC are input to all of the latches 510 _i (i is an integer from 1 through 8), as in the data input circuits 200 through 400 according to previous exemplary embodiments. For this reason, lines 560 for the data D<j> (j is an integer from 0 through 7) and the reference clock SC should be connected to the all of the latches 510 _i (i is an integer from 1 through 8). More specifically, the data input circuit 500 requires nine bus lines 560 and all of these bus lines 560 must be input to all of the latches 510 _i, so as to latch eight data D<j> with respect to the reference clock SC (i is an integer form 1 through 8 and j is an integer from 0 through 7).

FIG. 6 is a circuit diagram of a data input circuit 600 according to another exemplary embodiment of the present invention. Referring to FIG. 6, the data input circuit 600 includes eight latching units 610 _i (i is an integer from 1 through 8), eight data input buffers 640 _i (i is an integer from 1 through 8), a strobe signal input buffer 640 _ 9 , a repeater 650 , a first bus 661 , and a second bus 662 . In the case of the data input circuit 600 according to an exemplary embodiment, N shown in FIGS. 2 through 4 is eight.

In an exemplary embodiment, a reference clock SC is divided into two sub clocks SC_L and SC_R, and data D<0> through D<7> are divided into two sub data groups, i.e., D<0> through D<3> of a first sub data group and D<4> through D<7> of a second sub data group. The D<0> through D<3> of the first sub data group and D<4> through D<7> of the second sub data group are latched by the sub clocks SC_L and SC_R, respectively.

A data strobe signal DQS is buffered by the strobe signal input buffer 640 _ 9 and output to the two sub clocks, i.e., the first and second sub clocks SC_L and SC_R.

The data input buffers 640 _i (i is an integer from 1 through 8) buffer external data DQ 0 through DQ 7 and output them as internal signals, i.e., first through eighth data D<j> (j is an integer from 0 through 7). As mentioned, the first through fourth data D<0> through D<3>, and the fifth through eighth data D<4> through D<7> are classified into the first sub data group and the second sub data group, respectively.

Therefore, the first through fourth data D<0> through D<3> are latched in synchronization with the first sub clock SC_L, and the fifth through eighth data D<4> through D<7> are latched in synchronization with the second sub clock SC_R.

The first bus 661 is connected to the first through fourth latching units 610 _i (i is an integer from 0 through 3) that latch the first through fourth data D<j> (j is an integer from 1 through 4), respectively, and the second bus 662 is connected to the fifth through eighth latching units 610 _i that latch the fifth through eighth data D<j>, respectively (j is an integer from 4 to 7). Accordingly, it is possible to reduce the numbers and lengths of the bit lines.

Each of the eight latching units 610 _i includes one of the latches 620 _i and one of the dummy input units 630 _i (i is an integer from 1 through 8). The latches 620 _i latch one data D<j> of a corresponding sub data group in synchronization with a corresponding sub clock SC_L or SC_R (i is an integer from 1 through 8 and j is an integer from 0 through 7). More specifically, the first through fourth latch 620 _ 1 through 620 _ 4 latch the first data D<0>, the second data D<1>, the third data D<2>, and the fourth data D<3> of the first sub data group, respectively, in synchronization with the first sub clock SC_L. The fifth through eighth latch 620 _ 5 through 620 _ 8 latch the fifth data D<4>, the sixth data D<5>, the seventh data D<6>, and the eighth data D<7> of the second sub data group, respectively, in synchronization with the second sub clock SC_R. The dummy input units 630 _i may be any of the dummy devices described above in conjunction with other exemplary embodiments.

Each of the dummy input units 630 _i is a circuit to which data, except for data latched by a corresponding latch 620 _i, is input as dummy data (i is an integer from 1 through 8). More specifically, the first dummy input unit 630 _ 1 receives the data D<1> through D<3>, except for the first data D<0> latched by the first latch 620 _ 1 , of the first sub data group. For instance, the second dummy input unit 630 _ 2 receives the data D<0>, D<2>, and D<3>, except for the second data D<1> latched by the second latch 620 _ 2 , of the first sub data group. Likewise, the fifth dummy input unit 630 _ 5 receives the data D<5> through D<7>, except for the fifth data D<4> latched by the fifth latch 620 _ 5 , of the second sub data group. The sixth dummy input unit 630 _ 6 receives the data D<4>, D<6>, and D< 7 >, except for the sixth data D<5> latched by the sixth latch 620 _ 6 , of the second sub data group.

The first through fourth latching units 610 _ 1 through 610 _ 4 are connected to the first bus 661 , i.e., bus lines for the first through fourth data D<0> through D<3>, and a bus line for the first sub clock. The fifth through eighth latching units 610 _ 5 through 610 _ 8 are connected to the second bus 662 , i.e., bus lines for the fifth through eighth data D<4> through D<7>, and a bus line for the second sub clock. Accordingly, the data input circuit 600 according to an exemplary embodiment requires fewer and shorter bus lines connected to each latching unit. For example, nine bus lines are required in the data input circuit 500 but only five bus lines are required in the data input circuit 600 . Also, each bus line in the data input circuit 600 is a half as long as each bus line in the data input circuit 500 .

The repeating unit 650 is a circuit for amplifying the respective data D<j> (j is an integer from 0 through 7) and the first and second sub clocks SC_L and SC_R and includes ten repeaters. The number of the repeaters included in the repeating unit 650 is larger than that of the repeaters in the repeating unit 550 by one. Nevertheless, the length of each bus line connected to the repeaters 650 is a half of that of each bus line connected to the repeaters 550 , thereby reducing driving loads weighed on the repeater 650 . Therefore, power consumption in the data input circuit 600 is less than in the data input circuit 500 .

In the exemplary embodiment of FIG. 6, data is divided into two sub data groups but the number of sub data groups is not limited. If necessary, the number of sub data groups can be variously determined.

FIGS. 7 ( a ) and 7 ( b ) are diagrams illustrating examples of the strobe signal input buffer 640 _ 9 and data input buffer 640 _i (i is an integer from 1 through 8) which are shown in FIG. 6 .

The strobe signal input buffer 640 _ 9 includes a differential amplifier DA, a first sub clock generator 711 , and a second sub clock generator 712 . The differential amplifier DA compares a data strobe signal DQS with a reference voltage Vref and amplifies the data strobe signal DQS based on the comparison result so as to convert the data strobe signal DQS into an internal signal. The reference voltage Vref is a voltage signal of a predetermined level and may be an inversion signal DQSB of the data strobe signal DQS.

A signal output from the differential amplifier DA is input to the first and second sub clock generators 711 and 712 directly or via at least one inverter. The first and second sub clock generators 711 and 712 may be realized as at least one inverter. In an exemplary embodiment, the first and second sub clock generators 711 and 712 have the same or substantially the same structure, so that a delay time between an instant of time when the data strobe signal DQS is generated and a first sub clock SC_L, is the same as a delay time between the instant of time and a second sub clock SC_R.

The data input buffers 640 _i (i is an integer from 1 through 8) have the same or substantially the same structures and each of the data input buffer 640 _i includes a differential amplifier DA, a data generator 721 , and a dummy output unit 722 . In an exemplary embodiment, the structures of the data input buffers 640 _i are the same or substantially the same as that of the strobe signal input buffer 640 _ 9 .

The differential amplifier DA converts external data DQ into an internal signal by comparing the external data DQ with the reference voltage Vref and amplifying the external data DQ based on the comparison result. Here, the reference voltage Vref denotes a voltage signal of a predetermined level and may be the inversion signal DQB of the external data DQ.

A signal output from the differential amplifier DA is input to the data generator 721 and the dummy output unit 722 directly or via at least one inverter. The data generator 721 and the dummy output unit 722 may be realized as at least one inverter, and have the same or substantially the same structures as the first and second sub clock generators 711 and 712 . Using the dummy output unit 722 of the data input buffer 640 _i, it is possible to make a load weighed on the data input buffer 640 _i be identical or substantially identical with a load on the strobe signal input buffer 640 _ 9 that has the first and second sub clock generators 711 and 712 .

In an exemplary embodiment, a reference clock is divided into two sub clocks and data is classified into two sub data groups so as to reduce the length and number of bus lines, thereby reducing power consumption. Also, since the structure of each data input buffer is the same or substantially the same as that of a strobe signal input buffer that generates two sub clocks, a load between the reference clock and each data can be the same or substantially the same.

As described above, according to the present invention, it is possible to make a load on a reference clock be the same or substantially the same as that on each group of data in a circuit for latching multiple data with respect to the reference clock. Therefore, a load difference between the reference clock and each group of data is reduce to reduce a skew between the reference clock and each data. Also, the reference clock is divided into a plurality of sub clocks and multiple data is classified into a plurality of sub data groups so as to latch the multiple data per sub clock. Accordingly, a load difference between the reference clock and each data is reduced and power consumption is also reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.