Power/performance optimized cache using memory write prevention through write snarfing

A multiprocessor system may include two or more computer processors which may work together on a single program. Each processor may have its own cache memory which is separate from the larger system (or main) memory. A cache memory may be a portion of memory made of high-speed static random access memory (SRAM). Many programs may access the same data or instructions repeatedly. By keeping as much of this information as possible in the cache, the system may avoid accessing the slower system memory.

Cache coherency protocols may be employed to manage the caches of a multiprocessor system to prevent data from being lost or overwritten before the data is transferred from a cache to the system memory or from a cache to another cache. For example, in a system employing a snooping protocol, such as the MSI protocol, caches on the bus may monitor (or snoop) the bus to determine if they have a copy of the block of data requested on the bus. The caches may modify the state of a memory block they contain in a cache line from, e.g., modified (M) or dirty, shared (S), or invalid (I), in response to read or write operations taken by other caches on the bus.

FIG. 1 is a block diagram of a multiprocessor system which may employ a cache coherency protocol.

FIG. 2 is a block diagram of a system-on-chip (SoC) including multiple processors with separate caches.

FIG. 3 is a state diagram for a snooping cache coherency protocol.

FIG. 4 is a flowchart describing a write snarfing operation.

FIG. 1 illustrates a multiprocessor system 100 according to an embodiment. A number of cache-ownership capable agents 105 and cache-ownership incapable agents 110 may share a system bus 115 . The cache-ownership capable agents 105 and cache-ownership incapable agents 110 may access a system (or main) memory 120 through a memory controller 125 on the bus 115 .

The system 100 may be a system-on-chip (SoC) integrated circuit (IC) 200 , as shown in FIG. 2 . The SoC 200 may include different types of processors. Processors with write-back caches 205 may implement cache-ownership capable agents 110 . In write-back caching, data modifications (e.g., write operations) to data stored in the write-back cache 205 may not be copied to system memory 120 until necessary. In contrast, a write-through cache 210 may perform write operations in parallel, e.g., the write-though cache 210 may write data to system memory 120 and the write-through cache 210 simultaneously. Processors which have write-through caches or which do not have caches may implement cache-ownership incapable agents. Such processors may include, for example, Digital Signal Processing (DSP) devices, Direct Memory Access (DMA) devices, and Universal Serial Bus (USE) hosts.

When a cache-ownership incapable agent 110 wants to update a line, it may write the line directly to the system memory 120 . Other agents which wish to see the line may have to grab the line from the system memory 120 . In an SoC system, accessing system memory 120 may require off-chip, or even off-board, operations. Such operations may be slower and require more power than memory access operations to on-chip caches. For example, an off-board memory access may require a voltage step up to transmit through a high-voltage region, e.g., from about 0.5 V on-chip voltage to about 5 V, which may result in increased power consumption. External memory access may also increase address and data traffic in the system interconnect. If such write traffic occurs very often, it may consume significant amount of power.

External memory access such as memory writes may be reduced by utilizing data already stored in caches in the system. A cache-ownership capable agent may snarf data placed on the bus due to a write by a cache-ownership incapable agent, e.g., obtain the cache line corresponding to the memory line to be written from its own cache, if the required cache line is in a valid state in the agent's cache. This eliminates the cache-ownership capable agent from fetching the data again from the memory. Another mechanism is to let the write update cache only within a system without causing any memory write. The memory write may only occur when the cache line gets flushed or cleaned from the cache by a special instruction.

The system 100 may employ a cache coherency scheme to manage the caches of a multiprocessor system to prevent data from being lost or overwritten before the data is transferred from a cache to the system memory 120 . The system may employ a snooping cache coherency protocol. A snooping cache coherency protocol may include a snoop phase in which caches on the bus may monitor (or snoop) the bus to determine if they have a copy of a block of data requested on a bus, and a data phase in which the caches may modify the state of a memory block they contain in response to read or write operations taken by other caches on the bus.

FIG. 3 is a state diagram 300 illustrating an exemplary snooping protocol, e.g., an MSI protocol, in which the state of a memory block may transition between a modified (M) or dirty state 305 , a shared state (S) 310 (in which two or more caches may have copies), and an invalid state (I) 315 . A transaction may occur on the bus when a processor performs a read (PrRd) or a write (PrWt) operation. The MSI cache may snoop the bus on a bus transaction. The bus transactions may include requesting a copy of the memory block with no intent to modify (BusRd), requesting a copy with intent to modify (BusRdX), and updating memory (BusWB). BusRd may be used to service a miss, and BusRdX may be used to signal other caches about an impending write. Based on these actions, the MSI cache may update the state of the memory block, perform a bus transaction, or flush the memory block onto the bus.

A MESI protocol may introduce an exclusive state (E). A MESI cache may place a cache line in the exclusive state if that cache is the only cache with a copy of the cache line. The cache may modify the exclusive cache line without a bus transaction. A MOESI protocol may introduce an owned state (O). The owned state may be triggered when the data being requested is in more than one processors' cache and the data in one of those caches has been modified.

The agents 105 , 110 may communicate with each other using, for example, hit (HIT), hit/modified (HITM), and back-off (BOFF) signals. A HIT signal may be sent by an agent to indicate an address match if the line on the bus is in the exclusive (E) or shared (S) state. A logical OR operation may be performed on the HIT signals, and the OR'ed HIT may be sent back to every agent on the bus. A HITM signal may be sent by an agent to indicate an address match if the line on the bus is in a modified (M) or owned (O) state. The OR'ed HITM may also be sent to every agent on the bus. A BOFF signal may be sent to indicate that some agent which has the shared copy would like to intervene. Any other agents which have the shared copy may back off when a BOFF signal is asserted.

FIG. 4 shows a flowchart describing a write snarfing operation 400 . A cache-ownership incapable agent 110 may perform a write (block 405 ) and a write line command may be issued to the bus (block 410 ). During the snoop phase, if the agent is not a cache-ownership capable agent, then the agent may invalidate the cache line if it has a write-through cache 210 (block 415 ), or do nothing if the agent does not have a cache (block 420 ). If the agent is a cache-ownership capable agent 105 , the agent may snoop its cache 205 (block 425 ). If the address matches one of its tags, the agent may assert HIT=HITM=1 if the line is in the M/O state for a MOESI cache or if the line is in the M state for a MSI/MESI cache (block 430 ). The agent may assert HIT=1, HITM=0 if the line is in the E/S state for a MOESI/MESI cache or if the line is in S for a MSI cache (block 435 ). If the address does not match one of its tags, the agent may assert HIT=HITM=0 (block 440 ).

During the data phase, the agent that originated the write operation may put the data on the bus (block 445 ). The other agents on the bus may then take an appropriate action based on the type of cache coherency protocol (block 450 ), as shown in Table 1.

The memory snarfing operation 400 may prevent external memory transactions when a cache-ownership incapable agent performs a write operation on the bus and there is a valid copy in a Modified, Owned, Exclusive, or Shared state in any cache-ownership capable agent's cache. Preventing writes from going to system memory while there is a cached copy may reduce power consumption. The memory snarfing operation 400 may also lower the address/data traffic in the system interconnect and reduce the write latency by optimizing loads after a store operation, thereby improving the overall system performance.

The snarfing operation may be used with other cache coherency protocol support cache snooping.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, blocks in the flowchart may be skipped or performed out of order and still product desirable results. Accordingly, other embodiments are within the scope of the following claims.