Inventor

Samantha J. Edirisooriya

Inventor

Tempe, AZ, US

Overview

39→

Patents

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing71%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use25%

G11CStatic stores4%

PatentTitleYear

10,990,546Hardware-based virtual machine communication supporting direct memory access data transfer2021 10,810,138Enhanced storage encryption with total memory encryption (TME) and multi-key total memory encryption (MKTME)2020 10,679,690Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode2020 10,241,947Hardware-based virtual machine communication2019 10,235,302Invalidating reads for cache utilization in processors2019 10,127,968Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode2018 9,953,001Method, apparatus, and system for plugin mechanism of computer extension bus2018 8,533,401'Implementing direct access caches in coherent multiprocessors'2013 8,156,406'Method and system for syndrome generation and data recovery'2012 7,966,477'Power optimized replay of blocked operations in a pipilined architecture'2011 7,765,349'Apparatus and method for arbitrating heterogeneous agents in on-chip busses'2010 7,757,046'Method and apparatus for optimizing line writes in cache coherent systems'2010 7,725,683'Apparatus and method for power optimized replay via selective recirculation of instructions'2010 7,698,476'Implementing bufferless direct memory access (DMA) controllers using split transactions'2010 7,685,379'Cache memory to support a processor\'s power mode of operation'2010 7,640,387'Method and apparatus for implementing heterogeneous interconnects'2009 7,634,603'System and apparatus for early fixed latency subtractive decoding'2009 7,487,299'Cache memory to support a processor\'s power mode of operation'2009 7,464,227'Method and apparatus for supporting opportunistic sharing in coherent multiprocessors'2008 7,447,810'Implementing bufferless Direct Memory Access (DMA) controllers using split transactions'2008 7,428,607'Apparatus and method for arbitrating heterogeneous agents in on-chip busses'2008 7,406,552'Systems and methods for early fixed latency subtractive decoding including speculative acknowledging'2008 7,406,553'System and apparatus for early fixed latency subtractive decoding'2008 7,404,043'Cache memory to support a processor\'s power mode of operation'2008 7,366,845'Pushing of clean data to one or more processors in a system having a coherency protocol'2008 7,360,007'System including a segmentable, shared bus'2008 7,353,317'Method and apparatus for implementing heterogeneous interconnects'2008 7,343,546'Method and system for syndrome generation and data recovery'2008 7,330,998'Data integrity verification'2008 7,290,093'Cache memory to support a processor\'s power mode of operation'2007 7,234,028'Power/performance optimized cache using memory write prevention through write snarfing'2007 7,219,176'System and apparatus for early fixed latency subtractive decoding'2007 7,159,077'Direct processor cache access within a system having a coherent multi-processor protocol'2007 7,143,220'Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies'2006 7,100,001'Methods and apparatus for cache intervention'2006 7,062,613'Methods and apparatus for cache intervention'2006 6,983,348'Methods and apparatus for cache intervention'2006 6,775,748'Methods and apparatus for transferring cache block ownership'2004 6,247,157'Method of encoding data signals for storage'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to INTEL CORP (31)· patent assignee history

2001Based in Phoenix, AZ, US· patent location history

2004–2021Based in Tempe, AZ, US· patent location history

2007–2011Patents assigned to MARVELL INT LTD (8)· patent assignee history

2012–2013Patents assigned to EDIRISOORIYA SAMANTHA J (2)· patent assignee history

2013Patents assigned to JAMIL SUJAT (1)· patent assignee history

2013Patents assigned to MINER DAVID E (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	31	2001–2021
MARVELL INT LTD	8	2007–2011
EDIRISOORIYA SAMANTHA Jself	2	2012–2013
JAMIL SUJAT	1	2013
MINER DAVID E	1	2013

Locations

Location	Patents	Span
Tempe, AZ, US	38	2004–2021
Phoenix, AZ, US	1	2001