Semiconductor with a stress reduction layer and manufacturing method therefor

The present invention relates to a passivation layer in a semiconductor; and, more particularly, to a semiconductor with a stress reduction layer to prevent a passivation layer from being cracked during a packaging process and a manufacturing method therefor.

Generally, a passivation layer in a semiconductor acts as a protective coating to protect the underlying surface from physical and chemical reaction, e.g., scratch, corrosion, electro-dissolution, during a packaging process. Such passivation layer protects the semiconductor from being damaged by an environmental factor such as humidity. Such passivation layer is made of a combination of one or more oxide layers for stress reduction and one or more nitride layers for a protective coating.

For example, a plasma enhanced tetra ethyl ortho silicate (PETEOS) oxide layer is deposited on a substrate with a metal wiring by using the plasma enhanced chemical vapor deposition (PECVD) technique and further a SiH 4 nitride layer is deposited over the PETEOS oxide layer by using the PECVD technique to form a passivation layer. Alternatively, a SiH 4 oxide layer may be deposited by using the high density plasma (HDP) CVD technique and then a SiH 4 nitride layer may be deposited over the SiH 4 oxide layer by using the PECVD technique to form another passivation layer.

While a top metal wiring in a conventional semiconductor has a relatively thin thickness of about 5000 to 6000 angstroms, a top metal wiring in a semiconductor such as a multilayer wiring device or a power device has a thicker thickness of about 8000 to 10000 angstroms. Further, the top metal wiring in the power device extends to a wide region therein.

Such a passivation layer formed over the top metal wiring of the multiplayer wiring device or the power device may suffer from cracking, due to stress caused by an underlying metal wiring that are wide and thick. Therefore, there has been a long felt need for a stress resistant passivation layer having a low stress on the underlying metal wiring, as well as being robust to an external impact.

It is, therefore, an object of the present invention to provide a semiconductor with a stress reduction layer to prevent a passivation layer from being cracked during a packaging process and a manufacturing method therefor.

In accordance with one aspect of the present invention, there is provided a

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

FIGS. 1A to 1 C represent cross-sectional views for illustrating a manufacturing process of a semiconductor with a stress reduction layer in accordance with the present invention.

Referring to FIGS. 1A to 1 C, there is shown a method for manufacturing a semiconductor with a stress reduction layer in accordance with the present invention.

Referring to FIG. 1A, a substrate 10 , preferably a silicon substrate, is provided. It is known that an impurity injection layer such as a source and a drain, a gate electrode, an interlayer insulation layer and a metal wiring may be formed in the substrate 10 , although they have not been illustrated.

In a deposition process, e.g., a sputtering process, an Al metal layer (not shown) is deposited for a metal wiring 12 on the substrate 10 . Such Al metal layer preferably has a thickness of about 8000 to 10000 angstrom. A photoresist mask pattern (not shown) is formed over the Al metal layer, wherein the photoresist mask pattern corresponds to the metal wiring 12 as will be described thereinafter. The photoresist mask pattern is used to etch the Al metal layer to the substrate 10 so that the metal wiring 12 may be formed over a portion of the substrate 10 with the other portion of the substrate exposed. Although only two metal wirings 12 are shown in FIG. 1A, a number of metal wirings 12 may be formed on the substrate 10 .

Referring to FIG. 1B, the metal wiring 12 is subjected to a plasma process in N 2 O or O 2 atmosphere so that a thin metal oxide layer, e.g., an Al oxide layer, with a thickness of less than about 100 angstroms may be formed over the metal wiring 12 . Then, the thin metal oxide layer is annealed to form a stress reduction layer 14 . For example, the Al oxide layer may be annealed in an inert gas atmosphere of Ar, He or a combination thereof, as well as a gas atmosphere of N 2 O, O 2 , N 2 , H 2 or combinations thereof. The annealing process takes place at a lower temperature below about 400 degrees Celsius for about 10 minutes to about 24 hours, preferably for about 4 hours. Rapid thermal process or conventional furnace thermal process may be used. Accordingly, the metal wiring 12 with the stress reduction layer coated thereon may be formed over a portion of the substrate 10 while the other portion of the substrate 10 remains exposed.

Referring to FIG. 1C, a plasma enhanced chemical vapor deposition (PECVD) may be used to form a passivation layer 16 over the stress reduction layer 14 and the other portion, i.e., the exposed portion, of the substrate 10 . The thickness of the passivation layer 16 is preferably substantially equal to that of the metal wiring 12 so that the passivation layer 16 is about 8000 to 10000 angstroms in thickness. In case the metal wiring 12 is made of Al, the passivation layer 16 is preferably made of Al x O y composition. Further, it is preferable that the Al x O y composition has a major composition of Al 2 O 3 , which is thermally stable and has a lower stress against Al.

The passivation layer 16 may be annealed in an inert gas atmosphere of Ar, He or a combination thereof. Alternatively, the passivation layer 16 may be annealed in a gas atmosphere of N 2 O, O 2 , N 2 , H 2 or combinations thereof. The annealing process takes place at a lower temperature below about 400 degrees Celsius for about 10 minutes to about 24 hours, preferably for about 4 hours. Rapid thermal process or conventional furnace thermal process may be used. After the annealing process, the density of the passivation layer 16 increases so that the breakdown voltage of the passivation layer 16 may increase.

The stress reduction layer 14 reduces the stress on the passivation layer 16 , caused by the metal wiring 12 , while providing greater robustness. More specifically, the stress reduction layer 14 protects the passivation layer 16 from being cracked thus the leakage current of the semiconductor may be reduced and the breakdown voltage of the semiconductor may be increased.

While the invention has been shown and described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.