Semiconductor device having wide wiring pattern in outermost circuit

This application relates to and incorporates herein by reference Japanese patent application number 2002-41225, which was filed on Feb. 19, 2002.

This invention relates to technology of a terminal and wiring pattern layout when a semiconductor electronic part is mounted on a multilayer circuit board, and technology which enables wide and fine wiring patterns densely to be allocated.

There has been a semiconductor device, in which a control circuit IC packaged into a chip size package (CSP) as a control CSP is mounted on a circuit board. Here, the control CSP is connectable by using only a fine wiring pattern for transmitting a signal. Adoption of a multilayer (build-up) circuit board to the control CSP thereby leads to easy wiring design.

However, a CSP for engine control involves a wide wiring pattern for transmitting a power, which needs to find a different wiring design for an efficient layout of the wide wiring pattern.

To deal with the wide wiring pattern, it is proposed as shown in FIG. 7 . Here, a semiconductor electronic part 100 , a CSP, has a fine pitch, so that a corresponding multilayer circuit board 200 has lands 215 between which only one fine wiring pattern 216 b can pass as seen in the first layer 211 . When the CSP 100 is mounted on the multilayer circuit board 200 , wide wiring patterns 216 a and the corresponding lands 215 a are allocated without any specific consideration. Inefficiency of wiring allocation hence causes a broad area for allocating lands in an inner second layer 212 and useless lands 215 c of no wiring pattern connection. This leads to increase of the layer of the multilayer circuit board and disadvantage in costs.

It is therefore an object of the present invention to provide a semiconductor device in which an efficient wiring layout is enabled to prevent increase of a layer of a multilayer circuit board. Here, in the semiconductor device, a semiconductor electronic part has a fine pitch and terminals connectable with wide wiring patterns, being mounted on the multilayer circuit board. In the multilayer circuit board, only one fine wiring pattern is passable between lands.

To achieve the above object, a semiconductor device has a semiconductor electronic part in which terminals connectable with wide wiring patterns are allocated in at least the first outermost line among the terminals. Furthermore the semiconductor device has a multilayer circuit board in which lands linked with wide wiring patterns are allocated in at least the first outermost line of at least the first uppermost layer of the multilayer circuit board.

In one embodiment of the invention, a semiconductor device has a semiconductor electronic part in which terminals connectable with wide wiring patterns are allocated in the first and third outermost lines. Furthermore, here, the above terminals allocated in the first and third outermost lines are connectable with lands allocated in the first outermost lines of the first and second uppermost layers of the multilayer circuit board, respectively.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:

FIG. 1 is an exploded perspective view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a perspective view of a semiconductor electronic part of the first embodiment;

FIG. 3 is a vertical cross-sectional view of the semiconductor device of the first embodiment;

FIG. 4 is an exploded perspective view of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a vertical cross-sectional view of the semiconductor device of the second embodiment;

FIG. 6 is an exploded perspective view of a semiconductor device of a related art for comparison with the second embodiment; and

FIG. 7 is an exploded perspective view of a semiconductor device of a related art.

(First Embodiment)

Referring to FIGS. 1, 2 and 3 , a semiconductor device of a first embodiment is embodied in an IC (integrated circuit) of an engine control for vehicle driving. In this semiconductor device, a CSP (chip size package) 20 as a semiconductor electronic part is solder-mounted on a multilayer circuit board 10 . A plurality of bumps 22 (connecting terminals) are located in a checkered pattern on the substrate bottom 21 of the CSP 20 . The bumps 22 are located in a fine pitch.

The multilayer circuit board 10 has at least two layers of the first uppermost layer 11 as the front layer and the second uppermost layer 12 as the inner layer. In the multilayer circuit board 10 , wiring patterns 16 ( 16 a , 16 b ) and the lands 15 ( 15 a , 15 b ) are formed. Here, a first wiring pattern 16 b of the wiring patterns 16 is for transmitting a signal and linked with a second land 15 b of the lands 15 . Meanwhile a second wiring pattern 16 a of the wiring patterns 16 is for transmitting a power and linked with a second land 15 a of the lands 15 . The second wiring pattern 16 a is wider than the first wiring pattern 16 b . Only one first wiring pattern 16 b is passable between the lands 15 .

Bumps 22 a , parts of the bumps 22 in the CSP 20 , are connectable with the second land 15 a of the multilayer circuit board 10 , being allocated in the first outermost line L 1 among the bumps 22 . On the other hand, the second lands 15 a are allocated in the first outermost line L 1 of the first uppermost layer 11 of the multilayer circuit board 10 .

As shown in FIG. 3, a bump 22 a for transmitting the power is allocated in the first outermost line L 1 of the CSP 20 . It is then attached to a second land 15 a allocated in the first outermost line L 1 of the first uppermost layer 11 of the multilayer circuit board 10 . On the other hand, a bump 22 b , parts of the bumps 22 , for transmitting the signal is allocated in the second outermost line L 2 of the CSP 20 . It is then attached to a first land 15 b allocated in the second outermost line L 2 of the first uppermost layer 11 of the board 10 . Furthermore, the other bump 22 b for transmitting the signal, allocated in the third outermost line L 3 of the CSP 20 , is connected with a land 15 b of the second uppermost layer 12 through a via-hole of the first uppermost layer 11 . The bumps 22 b and 22 a are hence electrically connected with external terminals through the first and second wiring patterns 16 b (not shown in FIG. 3) and 16 a , respectively.

The wide second wiring pattern 16 a is thus drawn from the second land 15 a in the first outermost line L 1 of the first uppermost layer 11 . This avoids interference with other wiring patterns and ensures high efficiency of the wiring layout. This results in dispensing with an expensive multilayer circuit board of a lot of the layers even in the above case: The CSP 20 , having the fine-pitched bumps 22 connectable with the wide wiring patterns 15 a , is mounted on the multilayer circuit board 10 where only one fine wiring pattern 16 b is passable between the lands 15 .

The efficient wiring layout enables a land area used for a land layout to be smaller in the multilayer circuit board 10 . Namely, an area W 1 outside the land area in FIG. 1 can be larger than an area W 2 in FIG. 7 .

(Second Embodiment)

When the bumps 22 a for transmitting the power are more involved than in the above, the first embodiment may be modified to a second embodiment. At first, for the comparison with the second embodiment to be described later, a related art is explained referring to FIG. 6 . Here, Bumps for transmitting the power allocated in other than the odd-numbered outermost lines are connected with other than the first outermost line of each layer 311 , 312 , and 313 of a multilayer circuit board 300 . Here, the efficiency of wiring layout is decreased and a land area in the inner layers 312 and 313 of the multilayer circuit board 300 becomes larger than in the embodiments of the invention. Namely, a bump for transmitting the power is allocated also in the second outermost line so that the first uppermost layer 311 cannot provide the land for transmitting the power in the second outmost line L 2 in addition to the first outermost line L 1 . Therefore the first uppermost layer 311 has a land of no wiring pattern connection 315 c and the second uppermost layer 312 needs to have a land 315 a for transmitting the power. This results in decreasing the efficiency of the wiring layout in the first uppermost layer 311 . Furthermore, the second uppermost layer 312 has a land linked with a wide wiring pattern in the second outermost line L 2 in addition to the first outermost line L 1 . The number of the lands allocated in the first outermost line L 1 therefore decreases. This results in decreasing the efficiency of the wiring layout in the second uppermost layer 312 .

To improve the above inefficiency, the second embodiment is proposed. As shown in FIG. 4, bumps 22 a connectable with second lands 15 a may be allocated in the several odd-numbered outermost lines such as the first, third and fifth lines L 1 , L 3 and L 5 of the CSP 20 . Meanwhile, the second lands 15 a are allocated in the first outermost line L 1 of each of the layers 11 , 12 and 13 of the multilayer circuit board 10 . Namely, as shown in FIG. 5, the bumps 22 a connectable with the second lands 15 a are allocated in at least the first and third outermost lines L 1 and L 3 of the CSP 20 . The bumps 22 a allocated in the first and third outermost lines L 1 and L 3 are then attached to the second lands 15 a allocated in the first outermost lines L 1 of the first and second uppermost layers 11 and 12 of the multilayer circuit board 10 , respectively, also shown in FIG. 5 .

Specifically, a bump 22 a for transmitting the power allocated in the first outermost line L 1 of the CSP 20 is attached to a second land 15 a in the first outermost line L 1 of the first uppermost layer 11 . A bump 22 b for transmitting the signal allocated in the second outermost line L 2 of the CSP 20 is attached to a first land 15 b in the second outermost line L 2 of the first uppermost layer 11 . A bump 22 a for transmitting the power allocated in the third outermost line L 3 of the CSP 20 is connected with a second land 15 a in the first outermost line L 1 of the second uppermost layer 12 through a via-hole of the first uppermost layer 11 . A bump 22 b for transmitting the signal allocated in the fourth outermost line L 4 of the CSP 20 is connected with a first land 15 b in the second outermost line L 2 of the second uppermost layer 12 through a via-hole of the first uppermost layer 11 . Moreover, a bump 22 a for transmitting the power allocated in the fifth outermost line L 5 is connected with a second land 15 a in the first outermost line L 1 of the third uppermost layer 13 through the via-holes of the first and second uppermost layers 11 and 12 .

The wide second wiring patterns 16 a are thus drawn from the second lands 15 a in the first outermost lines L 1 of the layers 11 , 12 and 13 of the multilayer circuit board 10 . This avoids interference with other wiring patterns and ensures high efficiency of the wiring layout.