Semiconductor device having an oscillating circuit

This application claims the benefit of priority from prior Japanese Patent Application P2001-303086 filed on Sep. 28, 2001; the contents of which are incorporated by reference herein.

I. Field of the Invention

The present invention relates to a semiconductor device having an oscillating circuit. More particularly, the invention relates to a semiconductor device having a frequency oscillating circuit, such as an LC (which means “inductive-capacitive”) oscillating circuit.

II. Background of the Invention

The following will explain an example of the arrangement of a conventional oscillating circuit. FIG. 1 is a circuit diagram illustrating the conventional oscillation circuit arrangement.

In the oscillating circuit of FIG. 1, transistors Q 101 and Q 102 form a differential pair, and each base of the transistors Q 101 and Q 102 is connected to a collector of the other transistor. A coil L 101 and a capacitor C 101 , which form an LC resonant tank circuit, are connected between the collectors of these transistors Q 101 and Q 102 .

The collectors of transistors Q 101 and Q 102 are connected to a power supply voltage V DD via resistors R 101 and R 102 . A constant current source Io is connected to the emitters of transistors Q 101 and Q 102 . Moreover, the constant current source Io is connected to the ground potential GND. The output signal OUT 1 from the collector of the transistor Q 101 and an output signal OUT 2 from the collector of the transistor Q 102 are used as a differential pair output, or, alternatively, a single output of one side of the oscillating circuit (e.g., OUT 1 ) is used.

However, the aforementioned oscillating circuit can produce a signal at a fixed frequency, and has a problem in which the frequency cannot be varied.

Accordingly, the present invention is directed to a semiconductor device having a frequency oscillating circuit, such as an LC oscillating circuit.

A semiconductor device according to an embodiment of the present invention includes, for example, a first transistor having a control electrode and having one end and the other end of a current path thereof; a second transistor having a control electrode and having one end and the other end of a current path thereof, the control electrode is coupled to one end of the current path of the first transistor and one end of the current path thereof is coupled to the control electrode of the first transistor; a current mirror circuit that supplies a current to one end of the current path of the first transistor and one end of the current path of the second transistor; an inductor coupled to one end of the current path of the first transistor and one end of the current path of the second transistor; a first capacitor coupled to one end of the current path of the first transistor and one end of the current path of the second transistor; and a second capacitor and a switch element, are coupled to one end of the current path of the first transistor and one end of the current path of the second transistor.

A semiconductor device according to another embodiment of the present invention includes, for example, a first transistor having a control electrode and having one end and the other end of a current path thereof; a second transistor in which a control electrode is coupled to one end of the current path of the first transistor and one end of a current path thereof is coupled to the control electrode of the first transistor; a current mirror circuit that supplies a current to one end of the current path of the first transistor and one end of the current path of the second transistor; an inductor coupled to one end of the current path of the first transistor and one end of the current path of the second transistor; a constant current source coupled to the other end of the current path of the first transistor and the other end of the current path of the second transistor; a first capacitor coupled to one end of the current path of the first transistor and the other end of the constant current source; a second capacitor coupled to one end of the current path of the second transistor and the other end of the constant current source; a third capacitor and a first switch element coupled to one end of the current path of the second transistor and the other end of the constant current source; and a fourth capacitor and a second switch element coupled to one end of the current path of the second transistor and the other end of the constant current source.

Other features and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments and together with the description, serve to explain the principles of the invention. A more complete appreciation of the present invention and many of its attendant advantages will be readily obtained by reference to the following detailed description considered in connection with the accompanying drawings, in which:

FIG. 1 is a circuit diagram illustrating the arrangement of a conventional oscillating circuit;

FIG. 2 is a circuit diagram illustrating the arrangement of an oscillating circuit according to the first embodiment;

FIG. 3 is a circuit diagram illustrating the arrangement of an oscillating circuit of one modification of the first embodiment;

FIG. 4A is a circuit diagram illustrating the arrangement of an oscillating circuit of another modification of the first embodiment;

FIG. 4B is a circuit diagram illustrating the arrangement of an oscillating circuit of another modification of the first embodiment;

FIG. 5 is a circuit diagram illustrating the arrangement of an oscillating circuit according to the second embodiment;

FIG. 6 is a circuit diagram illustrating the arrangement of a control signal generating circuit in the oscillating circuit according to the second embodiment;

FIG. 7 is a circuit diagram illustrating another arrangement of the control signal generating circuit in the oscillating circuit according to the second embodiment; and

FIG. 8 is a circuit diagram illustrating the arrangement of a semiconductor laser driving circuit having an oscillating circuit.

The following will explain the embodiments of the present invention with reference to the accompanying drawings. In the description given below, wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

First, the oscillating circuit of the first embodiment of this invention will be explained. FIG. 2 is a circuit diagram illustrating the arrangement of an oscillating circuit according to the first embodiment of this invention.

As illustrated in FIG. 2, npn transistors Q 1 and Q 2 form a differential pair, and each base of the transistors Q 1 and Q 2 is connected to a collector of the other transistor, i.e., the base of transistor Q 1 is connected to the collector of Q 2 while the base of transistor Q 2 is connected to the collector of Q 1 .

A collector and a base of a pnp transistor Q 3 are connected to the collector of the transistor Q 1 . A collector of a pnp transistor Q 4 is connected to a collector of the transistor Q 2 . The arrangement of Q 3 and Q 4 is referred to herein as a current mirror which serves as a current source (or path).

A coil L 1 and a capacitor C 1 , which form an LC resonant tank, are connected in parallel between the collectors of the transistors Q 1 and Q 2 . Moreover, a capacitor C 2 and a switch S 1 are connected in series between the collectors of the transistors Q 1 and Q 2 .

A constant current source Io is connected to the emitters of transistors Q 1 and Q 2 . Moreover, the constant current source Io is connected to a reference potential terminal (for example, the ground potential GND). The emitters of the transistors Q 3 and Q 4 are connected to a power supply voltage VDD, respectively. Then, an output signal OUT is outputted from the collector of the transistor Q 2 .

In the above-arranged oscillating circuit, the capacitance value of the LC resonant tank is changed by turning ON/OFF the switch S 1 . The change of the capacitance value of the resonant tank variably changes an oscillation frequency of the output signal OUT.

Namely, the oscillating circuit shown in FIG. 2 has a differential amplifying circuit, which is composed of the npn transistors Q 1 , Q 2 and the pnp transistors Q 3 , Q 4 , which are active loads; the coil L 1 and the capacitor C 1 , which are connected in parallel between the collector of the transistor Q 1 and the collector of the transistor Q 2 ; and the capacitor C 2 and the switch S 1 , which are connected in series between the collector of the transistor Q 1 and the collector of the transistor Q 2 . Moreover, the constant current source Io is connected to the emitters of the transistors Q 1 and Q 2 , and the power supply voltage V DD is connected to the emitters of the transistors Q 3 and Q 4 .

According to the above-explained oscillating circuit, a constant of the LC resonant tank is decided depending on whether or not the coil L 1 , the capacitor C 1 , and the capacitor C 2 are incorporated into the circuit. In other words, by turning the switch S 1 ON or OFF, the time constant of the LC resonant tank is switched to “L 1 +C 1 ” or “L 1 +C 1 +C 2 .” This makes it possible to readily change the oscillation frequency of the output signal OUT.

Moreover, the oscillating circuit depicted in FIG. 2 uses the transistors Q 3 and Q 4 , which are active loads, in place of resistance loads R 101 and R 102 connected to the collectors of transistors Q 101 and Q 102 of the oscillating circuit of FIG. 1 . Accordingly, the oscillating circuit depicted in FIG. 2 makes it possible to increase the gain of differential amplifying circuit and to facilitate oscillation in the oscillating circuit.

Furthermore, as illustrated in FIG. 3, the oscillating circuit of FIG. 1 may be formed using MOS transistors in place of bipolar transistors. The oscillating circuit of FIG. 2 is one in which the npn transistors Q 1 and Q 2 and the pnp transistors Q 3 and Q 4 of the oscillating circuit shown in FIG. 1 are replaced with n-channel MOS transistors M 1 and M 2 and p-channel MOS transistors M 3 and M 4 , respectively. Otherwise, the arrangement and operation of FIG. 3 are similar to the oscillating circuit of the first embodiment shown in FIG. 2 .

In the oscillating circuit of FIG. 3, a switch S 1 may be formed using a transfer gate as illustrated in FIG. 4 A. This transfer gate is composed of an n-channel MOS transistor M 5 and a p-channel MOS transistor M 6 . In particular, a signal (labeled A) is input to the gate of the n-channel MOS transistor M 5 , and a signal (labeled Ā), which is a negative phase of the signal A, is input to the p-channel MOS transistor M 6 .

According to the oscillating circuit having the arrangement shown in FIG. 4A, when the signal A is set to be “L” in level (e.g., low level) and the signal Ā is set to be “H” in level (e.g., high in level), the transfer gate is interrupted (or opened). Resultantly, the constant of the LC resonant tank is set to “L 1 +C 1 .” When the signal A is set to be “H” in level and the signal Ā is set to be “L” in level, the transfer gate is conductive. Resultantly, the constant of the LC resonant tank is set to “L 1 +C 1 +C 2 .” In this way, the constant of the LC resonant tank is switched to “L 1 +C 1 ” or “L 1 +C 1 +C 2 ”, making it possible to easily change the oscillation frequency of the output signal OUT in this oscillation circuit.

The coil L 1 may be replaced with other inductors such as a quartz oscillator, as illustrated in FIG. 4B in which L 1 is replaced with Y 1 . Moreover, ceramic capacitors may be used as the capacitors C 1 and C 2 , and other capacitor, for example, a MOS capacitor may be used instead. Still moreover, the oscillating circuit of the first embodiment may be formed in the integrated circuit on the semiconductor substrate to make it possible to obtain oscillation at a more stable frequency.

As explained above, according to the first embodiment of the present invention, it is possible to provide an oscillating circuit that can vary the oscillation frequency according to the control signal that controls the ON/OFF of switch S 1 .

FIG. 5 is a circuit diagram illustrating the arrangement of an oscillating circuit according to the second embodiment of this invention. The same portions as those of the arrangement of the first embodiment of FIG. 3 are denoted by the same reference numerals and the explanation is omitted, and the following explains the different portions.

As illustrated in FIG. 5, a capacitor C 1 - 1 is connected between a drain of a MOS transistor M 1 and the ground potential GND. A capacitor C 1 - 2 is connected between a drain of the MOS transistor M 2 and the ground potential GND. Similarly, a capacitor C 2 - 1 and a MOS transistor S 2 - 1 are connected in series between the drain of the MOS transistor M 1 and the ground potential GND. A capacitor C 2 - 2 and a MOS transistor S 2 - 2 are connected in series between the drain of the MOS transistor M 2 and the ground potential GND. Moreover, a capacitor C 3 - 1 and a MOS transistor S 3 - 1 are connected in series between the drain of the MOS transistor M 1 and the ground potential GND. A capacitor C 3 - 2 and a MOS transistor S 3 - 2 are connected in series between the drain of the MOS transistor M 2 and the ground potential GND.

In one embodiment, the capacitance of the capacitor C 1 - 1 is equal to that of the capacitor C 1 - 2 . Similarly, the capacitance of the capacitor C 2 - 1 is equal to that of the capacitor C 2 - 2 , and the capacitance of the capacitor C 3 - 1 is equal to that of the capacitor C 3 - 2 -although any other combination of capacitance values may be used instead.

Namely, the capacitor C 1 - 1 , the capacitor C 2 - 1 and the MOS transistor S 2 - 1 , which are connected to each other in series, and the capacitor C 3 - 1 and the MOS transistor S 3 - 1 , which are connected to each other in series, are connected in parallel between the drain of the MOS transistor M 1 and the ground potential GND. Moreover, the capacitor C 1 - 2 , the capacitor C 2 - 2 and the MOS transistor S 2 - 2 , which are connected to each other in series, and the capacitor C 3 - 2 and the MOS transistor S 3 - 2 , which are connected to each other in series, are connected in parallel between the drain of the MOS transistor M 2 and the ground potential GND. In this way, in the oscillating circuit shown in FIG. 5, the capacitor and the coil are not connected to each other in parallel, but they are connected between each of both ends of the coil and the ground potential GND. Even if such a connection (as depicted in FIG. 5) is made, the effect is similar as in the case shown in FIG. 4A where the capacitor and the coil are connected in parallel.

Moreover, a control signal generating circuit 11 is connected to the gates of the MOS transistors S 2 - 1 , S 2 - 2 , S 3 - 1 and S 3 - 2 . The control signal generating circuit 11 generates control signals CS 1 and CS 2 that turn ON/OFF the MOS transistors S 2 - 1 , S 2 - 2 , S 3 - 1 , and S 3 - 2 . The control signal CS 1 is input to the gates of the MOS transistors S 2 - 1 and S 2 - 2 , and the control signal CS 2 is input to the gates of the MOS transistors S 3 - 1 and S 3 - 2 . When the control signals CS 1 and CS 2 are “L” in level, all the MOS transistors S 2 - 1 , S 2 - 2 , S 3 - 1 , and S 3 - 2 are turned OFF, and these MOS transistors are in a state where they are tuned off. At this time, the capacitance relating to oscillation becomes ½C, where C is equal to C 1 - 1 (which is also equal to C 1 - 2 ). Accordingly, the oscillating circuit outputs an output signal OUT having an oscillation frequency that is based on the coil L 1 and the capacitance ½C.

When the control signal CS 1 is “H” in level and the control signal CS 2 is “L” in level, the MOS transistors S 2 - 1 and S 2 - 2 are turned ON, and MOS transistors S 3 - 1 and S 3 - 2 are turned OFF. Resultantly, the MOS transistors S 2 - 1 and S 2 - 2 are in a state where they are tuned on, and the MOS transistors S 3 - 1 and S 3 - 2 are in a state where they are tuned off. At that time, the capacity relating to oscillation becomes “(C 1 +C 2 )/2.” Accordingly, the oscillating circuit outputs the output signal OUT having an oscillation frequency that based on the coil L 1 and the capacitance “(C 1 +C 2 )/2”.

When the control signals CS 1 and CS 2 are “H” in level, all of the MOS transistors S 2 - 1 , S 2 - 2 , S 3 - 1 , and S 3 - 2 are turned ON, and these MOS transistors fall in a turning on state. At this time, the capacity relating to oscillation becomes “(C 1 +C 2 +C 3 )/2.” Accordingly, the oscillating circuit outputs the output signal OUT having an oscillation frequency that is based on the coil L 1 and the capacitance “(C 1 +C 2 +C 3 )/2”.

An explanation will be next given of the specific circuit arrangement of the control signal generating circuit 11 .

FIG. 6 is a circuit diagram illustrating the arrangement of a control signal generating circuit. As illustrated in FIG. 6, a control signal generating circuit 11 comprises a circuit that generates a variable voltage V 1 , a circuit that generates reference voltages V 2 and V 3 , a comparator that compares the variable voltage V 1 with the reference voltage V 2 , and a comparator that compares the variable voltage V 1 with the reference voltage V 3 .

The circuit that generates the variable voltage V 1 is composed of a MOS transistor M 11 connected between a power supply voltage V DD and the ground potential GND, a resistor R 1 , and a variable resistor R 2 . The circuit that generates the reference voltages V 2 and V 3 is composed of a MOS transistor M 12 connected between the power supply voltage V DD and the ground potential GND, a resistor R 3 , a resistor R 4 , and a resistor R 5 .

The comparator, which compares the variable voltage V 1 with the reference voltage V 2 , is composed of MOS transistors M 15 to M 18 . The comparator, which compares the variable voltage V 1 with the reference voltage V 3 , is composed of MOS transistors M 25 to M 28 .

Moreover, the control signal generating circuit 11 has MOS transistors M 13 , M 14 , M 19 to M 24 , M 29 to M 32 , and a resistor R 6 connected thereto as illustrated in FIG. 6 .

In the control signal generating circuit 11 , control signals CS 1 and CS 2 are generated by the following operations. First, when the resistance value of the variable resistor R 2 is set, the variable voltage V 1 is decided by the MOS transistor 11 , which is connected between the power supply voltage V DD and the ground potential GND, the resistor R 1 , and the resistor R 2 according to the set resistance value of the resistor R 2 . Moreover, the reference voltages V 2 and V 3 are generated by the MOS transistor M 12 , which is connected between the power supply voltage V DD and the ground potential GND, and the resistors R 3 to R 5 .

The variable voltage V 1 and the reference voltage V 2 are input to the MOS transistors M 17 and M 18 that form the comparator. Then, the variable voltage V 1 and the reference voltage V 2 are compared by this comparator, and the control signal CS 1 is output by an inverter composed of MOS transistors M 22 and M 23 based on the comparison result.

Moreover, the variable voltage V 1 and the reference voltage V 3 are input to the MOS transistors M 25 and M 26 that form the comparator. Then, the variable voltage V 1 and the reference voltage V 3 are compared by this comparator, and the control signal CS 2 is output from an inverter composed of the MOS transistors M 31 and M 32 based on the comparison result.

As described above, the control signals CS 1 , CS 2 are used with three patterns in many cases: (CS 1 , CS 2 )=(L, L), (H, L), (H, H). In order to generate such patterns, the following relationship among the variable voltage V 1 and the reference voltages V 2 and V 3 must be established based on the following conditions:

When (CS 1 , CS 2 )=(L, L), V 2 <V 1 , and V 3 <V 1   (1)

When (CS 1 , CS 2 )=(H, L), V 3 <V 1 <V 2   (2)

When (CS 1 , CS 2 )=(H, H), V 1 <V 2 , and V 1 <V 3   (3)

In order to satisfy the above three conditions, the following relationships among the resistors R 1 to R 5 must be established. In order to satisfy condition (1), the relationships expressed by (R 4 +R 5 )/(R 3 +R 4 +R 5 )<R 2 /(R 1 +R 2 ) and by R 5 /(R 3 +R 4 +R 5 )<R 2 /(R 1 +R 2 ) are needed. In order to satisfy condition (2), the relationship expressed by R 5 /(R 3 +R 4 +R 5 )<R 2 /(R 1 +R 2 )<(R 4 +R 5 )/(R 3 +R 4 +R 5 ) is needed. Moreover, in order to satisfy condition (3), the relationships expressed by R 2 /(R 1 +R 2 )<(R 4 +R 5 )/(R 3 +R 4 +R 5 ) and by R 2 /(R 1 +R 2 )<R 5 /(R 3 +R 4 +R 5 ) are needed.

Moreover, although the control signal generating circuit 11 shown in FIG. 6 is a circuit that generates the two control signals CS 1 and CS 2 , the circuit of FIG. 6 may be expanded as illustrated in FIG. 7, so that a control signal generating circuit 12 that generates three control signals CS 1 , CS 2 , and CS 3 can be formed.

The control signal generating circuit 12 includes an additional resistor R 7 that is added to generate a reference voltage V 4 . Furthermore, a comparator, which is composed of MOS transistors M 34 to M 37 and which compares the variable voltage V 1 with the reference voltage V 4 , is added. Moreover, as shown in FIG. 7, MOS transistor M 33 and M 38 to M 41 are added.

The circuit arrangement of FIG. 7 may be further modified by adding additional components, which makes it possible to generate more than three control signals. In addition, the control signal generating circuit 12 may be used as the control signal generating circuit of FIG. 5 .

The use of the control signal generating circuit that generates numerous control signals makes it possible to add the number of pairs of capacitor and transistor connected in series to the oscillating circuit shown in FIG. 5 according to the number of control signals. This makes it possible to set the capacitance relating to resonance to more than three kinds of oscillation frequencies. Namely, the oscillating circuit of FIG. 7 with its three control signals CS 1 , CS 2 , CS 3 can vary the capacity relating to resonance by three kinds and produce the output signal OUT having three kinds of oscillation frequencies. However, if the capacitance relating to resonance can be set to more than three kinds, the oscillating circuit can produce the output signal OUT having more than three kinds of oscillation frequencies.

Similar to the first embodiment, the coil L 1 may be replaced with other inductors such as a quartz oscillator. Moreover, ceramic capacitors may be used as the capacitors C 1 - 1 , C 1 - 2 , C 2 - 1 , C 2 - 2 , C 3 - 1 and C 3 - 2 , and other capacitors, for example, a MOS capacitor may be used.

Still moreover, the oscillating circuit of the second embodiment is formed in the integrated circuit on the semiconductor substrate to make it possible to obtain oscillation at more stable frequency. Among the circuit elements that form the control signal generating circuits 11 and 12 , it is preferable that a variable resistor R 2 is placed at the outer portion of the integrated circuit and other circuit elements (except the variable resistor R 2 ) are placed in the integrated circuit. In this way, placement of variable resistor R 2 at the outer portion of the integrated circuit provides a means of readily changing the resistance value of the variable resistor R 2 .

As explained above, according to the second embodiment of the present invention, it is possible to provide an oscillating circuit that can vary the oscillation frequency by changing the resistance value of the resistor R 2 in the control signal generating circuit.

FIG. 8 is a circuit diagram illustrating the arrangement of the semiconductor laser driving circuit having the oscillating circuit. Either of the oscillating circuits of the first and the second embodiments may be used in a semiconductor laser driving circuit. This semiconductor laser driving circuit is formed on a semiconductor substrate. Here, it is assumed that the semiconductor laser is used at the time of reading and writing in, for example, a compact disc device (CD-R/RW).

As illustrated in FIG. 8, a voltage Vrin for setting a read current Ir is converted into a current by a voltage-current converting circuit (V/I converting circuit), and the resultant is input to a current output circuit (Driver) D 1 . There are two kinds of write currents. A voltage Vw 1 in for setting a first write current Iw 1 is converted to a current by a voltage-current converting circuit V 12 , and the resultant is input to a current output circuit D 2 . A voltage Vw 2 in for setting a second write current Iw 2 is converted to a current by a voltage-current converting circuit V 13 , and the resultant is input to a current output circuit D 3 . The read current Ir is a current that is used at a reading time, and write currents Iw 1 and Iw 2 are currents that are used at a writing time.

A logic input signal LOIN is input to a logic processing circuit 21 . The logic processing circuit 21 outputs a signal, which controls the presence or the absence of the operation of an oscillating circuit 22 , to the oscillating circuit 22 according to the input logic input signal LOIN. Also, the logic processing circuit 21 outputs a signal, which controls whether or not the read current Ir, the write current Iw 1 , the write current Iw 2 are to be output, to the current output circuits D 1 , D 2 , and D 3 .

Moreover, a ground potential is supplied to a control signal generating circuit 11 via a resistor Rfadj, and the control signal generating circuit 11 outputs control signals CS 1 and CS 2 , which are used to control an oscillation frequency fixed by the resistor Rfadj, to the oscillating circuit 22 . The oscillating circuit 22 outputs a signal with an oscillation frequency, which is responsive to the control signals CS 1 and CS 2 , to a current output circuit D 4 .

The ground potential is supplied to the current output circuit D 4 via a resistor Raadj. The resistor Raadj decides amplitude of the current that the current output circuit D 4 outputs. Accordingly, the current output circuit D 4 outputs a current Ihfm with amplitude, which is fixed by an oscillation frequency output from the oscillation circuit 22 and the resistor Raadj.

At the time of reading, a current lout, which is generated by the read current Ir and the current Ihfm, is supplied to a laser diode LD. Moreover, at the time of writing, the write current Iw 1 is changed to the current lout, and is supplied to the laser diode LD. Or, the current lout, which is generated by the write current Iw 1 and the write current Iw 2 , is supplied to the laser diode LD. Then, the laser diode LD varies intensity of light-emission according to the oscillation frequency of the current lout and amplitude.

In the aforementioned semiconductor laser driving circuit, the oscillation frequency output from the oscillating circuit 22 can be varied by the control signals CS 1 and CS 2 output from the control signal generating circuit 11 . This makes it possible to change the oscillation frequency of the current lout to be supplied to the laser diode LD and to vary the state of light-emission of the laser diode LD.

Moreover, the aforementioned embodiments include a plurality of structural elements that may be appropriately combined in various combinations.

As mentioned above, according to the present invention, there can be provided an oscillating circuit, which is capable of varying the oscillation frequency according to the control signal, and the semiconductor device having such an oscillating circuit.