Broadband sample and hold circuit

The present invention relates to circuits and more particularly to a broadband sample and hold circuit.

Sample and hold circuits are used for sampling values of continuous time-varying amplitude signals at discrete time intervals. The sample and hold circuits can be employed as part of an analog-to-digital signal conversion process, such that the amplitude values of analog input signals are sampled at timed intervals and converted into digital values to provide a digital output representation of the time varying amplitude signal. FIG. 1 illustrates a conventional sample and hold circuit 10 employing a sampling capacitor C and an operational amplifier 12 . The operational amplifier 12 is provided as an output buffer. A continuous time-varying amplitude input signals V IN (e.g., AC sine wave) is applied to the sampling capacitor C during a sample phase in which sample switches SA and SB are closed and a hold switch HA is open. The sampling capacitor C is connected to the input signal V IN through the sample switch SA and to ground through the sample switch SB. The sampling capacitor C charges to an amplitude level of the input signal V IN at the sampling interval, which is held by the capacitor C, and provided at an output of the operational amplifier 12 during a hold phase in which the sample switches SA and SB are opened and the hold switch HA is closed. The switches SA, SB and HA are controlled by a timing or clocking signal so that a plurality of samples can be taken of the input signal to determine various amplitude levels of the input signal, and a piecewise approximation of the input signal can be determined and converted to a digital representation of the analog input signal.

The sample and hold switches are typically implemented employing Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs). In the conventional sample and hold circuits, the signals that control the switching of the sample and hold switches or MOS transistors are simple digital signals (e.g., 0, V DD ). The “ON” resistance of the MOSFET is the resistance between the source region and the drain region when the transistor is “ON” or conducting, which is a function of the gate to source voltage V GS and the source to back gate voltage V SB . Therefore, the resistance of the input sampling switch varies with the input signal level. This causes the voltage across the capacitor C at the sampling instant to change with the amplitude of the input signal due to the non-linearity of the sampling switches. One solution to this problem is to employ a clock boosting circuit which ensures that the gate to source bias of the sampling switch is independent or a function of the signal amplitude, and that the gate to source voltage is held above the input signal or relatively constant reducing the non-linearity in the MOSFET switch.

Another problem is that as the input signal frequency increases, the AC currents flowing through the sampling switches increase. Therefore, the voltage drop across the switch resistances increase. MOSFET devices will enter non-linear resistor regions unless the voltage across the devices remains low. If the current through the switches remains within the linear region, the large voltages do not cause large voltage drops across the MOSFET switches. One solution would be to employ MOSFET devices with very large width to length ratios (W/L), thus, reducing their resistances. However, this increases the parasitic capacitances at the switch terminals. This in turn affects the speed of operation of the circuit. Also, the loading on the clock drivers increases, again effecting the speed of operation of the circuit.

In wireless receivers (e.g., broadband modem receivers) the voltage amplitudes and frequencies are relatively high causing the AC currents flowing through the sampling switches to be relatively high. In some applications employing wireless receivers, the input frequency can be much higher than the amplifier sampling frequency. These wireless receivers require sample and hold devices with input bandwidths that are much larger than the sampling frequency to facilitate direct demodulation of the radio frequency signals.

The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

The present invention relates to sample and hold devices in which an input sample switch couples an input voltage signal to a first end of a sampling capacitor and a hold switch couples the sampling capacitor to an output terminal. The input sample switch can be, for example, a MOSFET switch. The MOSFET switch will enter non-linear resistor regions unless the voltage across the switch remains low. The present invention provides for an alternate path with respect to a path through the input sample switch through which a replicated current is generated and directed or steered into the first end of the capacitor during a sample phase to mitigate the deleterious effects of high currents through the input sample switch. If a ground sample switch is employed to couple a second end of the sampling capacitor to ground, a second current is replicated that discharges current through a second alternate path from the second end of the capacitor to mitigate the deleterious effects of high currents through the ground sample switch.

In one aspect of the invention, a first current mirror having a first capacitor draws current from the input voltage signal that is a replicate of a current required to charge the sampling capacitor to the sampled voltage. The first capacitor has a capacitive value substantially equivalent to the capacitive value of the sampling capacitor, so that the current drawn from the input signal by the first capacitor is substantially equivalent to the current required to charge the sampling capacitor. The replicated current is directed or steered into the first end of the sampling capacitor through a first alternate path with respect to a path through the input sample switch. The first current mirror provides a low impedance path for the replicated current to facilitate redirection of the input current from the input sample switch. The first current mirror can cooperate with a first current source to generate the replicated current.

If a ground sample switch is employed, a second current mirror having a second capacitor draws current from an inverted version of the input voltage signal that is a replicate of a current required to charge the sampling capacitor to the sampled voltage. The second capacitor has a capacitive value substantially equivalent to the capacitive value of the sampling capacitor, so that the current drawn from the input signal by the second capacitor is substantially equivalent to the current required to charge the sampling capacitor. The replicated current is directed or steered out of the second end of the sampling capacitor through a second alternate path with respect to a path through the ground sample switch. The second current mirror provides a low impedance path for the replicated current to facilitate redirection of the input current from the input sample switch. The second current mirror can cooperate with a second current source to generate the replicated current. The inverted version of the input signal can be provided employing an inverting amplifier, or from a negative rail of a differential input signal if the input voltage signal is differential.

These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

FIG. 1 illustrates a schematic diagram of a prior art sample and hold device.

FIG. 2 illustrates a schematic block diagram of a sample and hold device in accordance with an aspect of the present invention.

FIG. 3 illustrates a schematic block diagram of a sample portion of a sample and hold device in accordance with an aspect of the present invention.

FIG. 4 illustrates a schematic block diagram of a sample circuit of a sample and hold circuit in accordance with an aspect of the present invention.

FIG. 5 illustrates a graph of voltage versus time of exemplary simulated output waveforms on a sampling capacitor in accordance with an aspect of the present invention.

FIG. 6 illustrates a graph of voltage versus time of exemplary simulated waveforms across an input signal sample switch during a sampling phase in accordance with an aspect of the present invention.

FIG. 7 illustrates a graph of decibels versus frequency of exemplary simulated output spectra on a sampling capacitor in accordance with an aspect of the present invention.

FIG. 8 illustrates a block diagram of a wireless receiver employing a sample and hold device in accordance with an aspect of the present invention.

FIG. 9 illustrates a methodology for operating a sample and hold device in accordance with an aspect of the present invention.

The present invention relates to sample and hold devices in which switches are employed to switch between a sample phase and a hold phase. During a sample phase, one or more sample switches are closed so that an input signal is applied to a sampling capacitor. The capacitor charges to a voltage amplitude level of the input signal level at the sampling interval. During a hold phase, the one or more sample switches are opened and one or more hold switches are closed, so that the voltage level of the charged capacitor is provided at an output terminal. The sampling capacitor requires currents to charge the capacitor to the amplitude of the input signal level, which can be substantially high at high input signal voltage levels and frequencies. The AC current flowing into the capacitor also flows out of the capacitor to ground. The high AC currents cause non-linearity in the sample switches during the sample phase. The present invention provides for replications of the current drawn by the sampling capacitor through samples switches and steers the replicated currents through alternate paths to mitigate the deleterious effects of the high AC currents through the sample switches.

FIG. 2 illustrates a sample and hold device 20 in accordance with an aspect of the present invention. The sample and hold device 20 includes a sampling capacitor C A coupled between a negative input terminal of an operational amplifier 22 through a node “B”, and an input signal sample switch (S 1 ) 28 through a node “A”. A ground sample switch (S 2 ) 30 is connected between the node “B” and ground. A hold switch (H 1 ) 32 is coupled between the node “A” and an output terminal 33 of the operational amplifier 22 . The input signal sample switch (S 1 ) 28 , the ground sample switch (S 2 ) 30 and the hold switch (H 1 ) 32 , for example, are MOSFET devices.

The sample and hold device 20 includes a first AC current mirror 24 and a second AC current mirror 26 coupled to an input terminal 21 . The first AC current mirror 24 is connected to node “A” through a switch (S 3 ) 34 , and the second AC current mirror 26 is connected to node “B” through a switch (S 4 ) 36 . The first and second AC current mirrors 24 and 26 mirror or replicate the current drawn by the sampling capacitor C A , and steer the replicated current through alternate current paths, so that the current through the sample switches S 1 and S 2 is mitigated, while still providing the necessary current to charge the sampling capacitor C A . The first AC current mirror 24 and the second AC current mirror 26 provide low impedance paths to draw the current required to charge the sampling capacitor C A along alternate paths. The alternate current paths minimize the current through the sample switches S 1 and S 2 which mitigates the effects of high current through the sample switches, and thus, the effects of non-linear resistances of the sample switches S 1 and S 2 .

A continuous time-varying amplitude input signal V IN (e.g., AC sine wave) is applied at the input terminal 21 . During a sample phase, sample switches S 1 and S 2 are closed and switches S 3 and S 4 are closed. The sampling capacitor C A is connected to the input signal V IN through the sample switch S 1 , and to ground through the sample switch S 2 . The AC current required to charge the sampling capacitor C A is drawn or replicated by the first AC current mirror 24 as IS A1 . and similarly by the second AC current mirror 26 as IS A2 . The first AC current mirror 24 provides or steers a reflected version IS A2 of the current IS A1 to the node “A” to provide the current necessary to charge the sampling capacitor C A through an alternate path than the path through the sample switch S 1 . The second AC current mirror 26 provides or steers a reflected version IS B2 of the current IS B1 from the node “B” to remove the discharge current from the sampling capacitor C A through an alternate path than through the sample switch S 2

Therefore, the current through both sample switches S 1 and S 2 is mitigated such that the high currents required to charge the sampling capacitor C A at high frequencies do not flow through the sample switches S 1 and S 2 , but flow through alternate paths. Therefore, the voltage drops across the switches S 1 and S 2 are mitigated. The sampling capacitor C A charges to an amplitude level of the input signal V IN at the sampling interval, which is held by the capacitor C A and provided at the output terminal 33 of the operational amplifier 22 during a hold phase in which sample switches S 1 and S 2 and switches S 3 and S 4 are opened and hold switch H 1 is closed. It is to be appreciated that in certain sample and hold device, the capacitor is directly connected to ground and the sample ground switch is eliminated. In this sample and hold device configuration, the first AC current mirror 24 can be employed without the second AC current mirror 26 .

FIG. 3 illustrates a sample portion 50 of a sample and hold device operative to receive a single ended input signal in accordance with an aspect of the present invention. The sample portion 50 includes a first current source 52 and a first AC current mirror 56 that cooperate to provide current to a sampling capacitor C 1 , and a second current source 54 and a second AC current mirror 58 that cooperate to remove current from the sampling capacitor C 1 . The sampling capacitor C 1 is coupled between a first node “A” and a second node “B”. An input signal sample switch (S 5 ) 60 is coupled between an input signal terminal 51 and the first node “A”, and a ground sample switch (S 6 ) 62 is connected between the second node “B” and ground. The sample switches S 5 and S 6 , for example, are MOSFET devices. The input signal sample switch S 5 and the ground sample switch S 6 are closed during a sample phase in which an input signal voltage V IN+ is provided at the first node “A” to charge the capacitor C 1 to the voltage amplitude level of the voltage V IN+ .

The first AC current mirror 56 is comprised of a first n-type MOSFET device M 1 and a second MOSFET device M 2 arranged as a cascode current source, and a capacitor C 2 . The gate of the first n-type MOSFET device M 1 is coupled to a bias voltage V B1 and the gate of the second n-type MOSFET device M 2 is coupled to a bias voltage V B2 , such that the n-type MOSFET devices M 1 and M 2 are held in a saturation region and carry a current equal to I 1 . The first n-type MOSFET device M 1 has a drain coupled to a switch (S 8 ) 66 and the second n-type MOSFET device M 2 has its source coupled to ground. The source of the first n-type MOSFET device M 1 and the drain of the second n-type MOSFET device M 2 are coupled to a first end of the capacitor C 2 through a node 57 . The other end of the capacitor C 2 is connected to the input signal terminal 51 . The input signal V IN+ is also provided at an inverted operational amplifier 72 , such that the inverted version of the input signal is provided at a capacitor C 3 .

The second AC current mirror 58 is comprised of a third n-type MOSFET device M 3 and a fourth MOSFET device M 4 arranged as a cascode current source, and the capacitor C 3 . The gate of the third n-type MOSFET device M 3 is coupled to a bias voltage V B3 and the gate of the fourth n-type MOSFET device M 4 is coupled to a bias voltage V B4 , such that the n-type MOSFET devices M 3 and M 4 are held in a saturated region and carry a current equal to I 2 . The third n-type MOSFET device M 3 has a drain coupled to a switch (S 10 ) 70 and the fourth n-type MOSFET device M 4 has its source coupled to ground. The source of the third n-type MOSFET device M 3 and the drain of the fourth n-type MOSFET device M 4 are coupled to a first end of the capacitor C 3 through a node 59 . The other end of the capacitor C 3 is connected to the output of the operational amplifier 72 . The capacitor C 2 is substantially equal to the capacitor C 1 , and the capacitor C 3 is substantially equal to the capacitor C 1 , such that the AC current drawn by the capacitor C 2 and C 3 are substantially equal to the AC current drawn by the capacitor C 1 during a sample phase.

During a sample phase, switches S 5 -S 10 are closed and an input signal V 1N+ is applied to the sample portion 50 of the sample and hold device. An input signal is applied to the terminal 51 , while an inverted version of the input signal is applied to the capacitor C 3 . The sampling capacitor C 1 is connected to the input signal V 1N+ through the sample switch S 5 and to ground through the sample switch S 6 . With zero input signal (I SIG =0), the signal currents in C 1 and C 2 would both be zero. Thus, all the current I 1 supplied by the current source 52 flows through M 1 and through M 2 . Thus, there is no net current flow into node “A”. With an input signal I SIG present, the node 57 acts as a virtual ground, the current flowing in C 1 is also replicated in C 2 . This steers away a substantially equal amount of current from the current supplied by M 1 . Since M 2 has a fixed bias voltage at the gate and a fixed source voltage (ground), the current through M 2 cannot change and remains at I 1 . The current through M 1 becomes I 1 −I SIG which provides a net current of I SIG into the node “A”. This provides the charging current for C 1 and mitigates the amount of current flowing through the input sampling switch S 5 .

In a similar fashion, the capacitor C 3 in conjunction with the M 3 and M 4 helps remove a current I SIG from node B, thus mitigating the current flowing through the ground sampling switch S 6 . Specifically, with zero input signal (I SIG =0), the signal currents in C 1 and C 3 would both be zero. Thus, all the current I 2 supplied by the current source 54 flows through M 3 and through M 4 . With the input signal I SIG present, the node 59 acts as a virtual ground, the current flowing out of C 1 is also replicated by C 3 . This steers a substantially equal amount of current into the current supplied by M 3 . Since M 4 has a fixed bias voltage at the gate and a fixed source voltage (ground), the current through M 4 cannot change and remains at I 2 . The current through M 3 becomes I 2 +I SIG which provides a net current of I SIG out of the node “B”.

The AC current mirrors 56 and 58 provide low impedance paths for the replicated currents. Therefore, the currents through both sample switches S 5 and S 6 are redirected such that the high currents required to charge the sampling capacitor C 1 at high frequencies do not flow through the sample switches S 5 and S 6 but flow through alternate paths. Therefore, the voltage drops across the switches S 5 and S 6 are mitigated since the switches operate in the linear region. The first and second AC current source and mirror combinations provide alternate current paths for the sample portion 50 of the sample and hold device, so that the current through the sample switches S 5 and S 6 are reduced, while still providing the necessary current to charge the sampling capacitor C 1 .

FIG. 4 illustrates a sample circuit 80 of a sample and hold circuit operative to receive a differential input signal in accordance with an aspect of the present invention. The sample circuit 80 of the sample and hold circuit include a first current source 82 and a first AC current mirror 86 that cooperate to provide current to a sampling capacitor C 4 , and a second current source 84 and a second AC current mirror 88 that cooperate to remove current from the sampling capacitor C 4 . The sampling capacitor C 4 is coupled between a first node “A” and a second node “B”. A first n-type MOSFET switch M 5 is coupled between a positive rail input signal terminal 81 and the first node “A”, and a second n-type MOSFET switch M 6 is connected between the second node “B” and ground. The first n-type MOSFET switch M 5 and the second n-type MOSFET switch M 6 provide input signal switching and ground connections to the sampling capacitor C 4 during a sample phase of the sample and hold circuit. A control signal S CONTROL controls the switching of the first n-type MOSFET switch M 5 and the second n-type MOSFET switch M 6 between an “ON” and an “OFF” state. It is to be appreciated that the first n-type MOSFET switch M 5 and the second n-type MOSFET switch M 6 can be replaced with p-type devices in which the control signal switches between opposite digital states than for n-type devices.

The first current source 82 is comprised of a first p-type MOSFET device M 7 and a second p-type MOSFET device M 8 arranged as a cascode current source, while the second current source is comprised of a third p-type MOSFET device M 11 and a fourth p-type MOSFET device M 12 arranged as a cascode current source. The gates of the p-type MOSFET device M 7 , M 8 , are coupled to bias voltages V B7 , V B8 , respectively, to be held in a saturation region and carry a current equal to I 3 . The gates of the p-type MOSFET device M 11 , M 12 , are coupled to bias voltages V B11 , V B12 , respectively, to be held in a saturation region and carry a current equal to I 4 . The first current source 82 and the second current source 84 are coupled to a supply voltage V DD and provide a constant current to the nodes “A” and “B” through a switch (S 11 ) 92 and a switch (S 13 ) 96 , respectively. The first AC current mirror 86 is comprised of a first n-type MOSFET device M 9 and a second MOSFET device M 10 arranged as a cascode current source, and a capacitor C 5 . The first n-type MOSFET device M 9 has a drain coupled to a switch (S 12 ) 94 and the second n-type MOSFET device M 10 has its source coupled to ground. The source of the first n-type MOSFET device M 9 and the drain of the second n-type MOSFET device M 10 are coupled to a first end of the capacitor C 5 through a node 87 . The other end of the capacitor C 5 is connected to the positive rail input signal terminal 81 .

The second AC current mirror 88 is comprised of a third n-type MOSFET device M 13 and a fourth MOSFET device M 14 arranged as a cascode current source, and a capacitor C 6 . The third n-type MOSFET device M 13 has a drain coupled to a switch (S 14 ) 98 and the fourth n-type MOSFET device M 14 has its source coupled to ground. The source of the third n-type MOSFET device M 13 and the drain of the fourth n-type MOSFET device M 14 are coupled to a first end of the capacitor C 6 through a node 89 . The gates of the n-type MOSFET device M 9 , M 10 , M 13 and M 14 are coupled to bias voltages V B9 , V B10 , V B13 , V B14 , respectively, to be held in a saturation region. The other end of the capacitor C 6 is connected to a negative rail input signal terminal 90 . The capacitor C 5 is substantially equal to the capacitor C 4 , and the capacitor C 6 is substantially equal to the capacitor C 4 , such that the AC current drawn by the capacitor C 5 and C 6 are substantially equal to the AC current drawn by the capacitor C 4 during a sample phase.

During a sample phase, sampling transistors M 5 and M 6 are turned “ON” and switches S 11 -S 14 are closed. A positive rail input signal V IN+ is applied to the sampling capacitor C 4 at the node “A” through the MOSFET switch M 5 . With zero input signal (I SIG =0), the signal currents in C 4 and C 5 would both be zero. Thus, all the current I 3 supplied by the current source 82 flows through M 9 and through M 10 . Thus, there is no net current flow into node “A”. With an input signal I SIG present, the node 87 acts as a virtual ground, the current flowing in C 4 is also replicated in C 5 . This steers away a substantially equal amount of current from the current supplied by M 9 . Since M 10 has a fixed bias voltage at the gate and a fixed source voltage (ground 0 , the current through M 10 cannot change and remains at I 3 . The current through M 9 becomes I 3 −I SIG which provides a net current of I SIG into the node “A”. This provides the charging current for C 4 and mitigates the amount of current flowing through first n-type MOSFET switch M 5 .

A negative rail input signal V IN− is provided at the capacitor C 6 . In a similar fashion, the capacitor C 6 in conjunction with the M 13 and M 14 helps remove a current I SIG from node B, thus mitigating the current flowing through second n-type MOSFET switch M 6 . Specifically, with zero input signal (I SIG =0), the signal currents in C 4 and C 6 would both be zero. Thus, all the current I 4 supplied by the current source 84 flows through M 13 and through M 14 . With the input signal I SIG present, the node 89 acts as a virtual ground, the current flowing out of C 4 is also replicated by C 6 . This steers a substantially equal amount of current into the current supplied by M 13 . Since M 14 has a fixed bias voltage at the gate and a fixed source voltage (ground), the current through M 14 cannot change and remains at I 4 . The current through M 13 becomes I 4 +I SIG which provides a net current of I SIG out of the node “B”.

FIG. 5 illustrates a graph 100 of voltage (volts) versus time (microseconds) of exemplary simulated output waveforms on a sampling capacitor in response to a 1 V PP input signal at 201 MHZ and a sampling frequency of 50 MHZ. A waveform 102 illustrates an output voltage waveform on a sampling capacitor of a sample and hold device employing a current mirror to steer current into a sampling capacitor along an alternate path with respect to a path through an input switch to the sampling capacitor. A waveform 104 illustrates an output voltage on a sampling capacitor of a conventional sample and hold device. The sampled voltage is about 0.1 volts higher employing an alternate path through an input switch to the sampling capacitor.

FIG. 6 illustrates a graph 120 of voltage (volts) versus time (nanoseconds) of exemplary simulated waveforms across an input signal sample switch during a sampling phase in response to a 1 V PP input signal at 201 MHZ and a sampling frequency of 50 MHZ. A waveform 122 illustrates an output voltage waveform across an input sample switch of a sample and hold device employing a current mirror to steer current into a sampling capacitor along an alternate path with respect to a path through an input switch to the sampling capacitor. A waveform 124 illustrates an output voltage waveform across a sample switch of a conventional sample and hold device. The voltage across the conventional device is substantially higher than the device employing an alternate path through an input switch to the sampling capacitor.

FIG. 7 illustrates a graph 140 of decibels (DB) versus frequency (MegaHertz) of exemplary simulated output spectra on a sampling capacitor in response to a 1 V PP input signal at 201 MHZ and a sampling frequency of 50 MHZ. A waveform 142 illustrates an output spectrum on a sampling capacitor of a sample and hold device employing a current mirror to steer current into a sampling capacitor along an alternate path with respect to a path through an input switch to the sampling capacitor. A waveform 144 illustrates an output spectra on a sampling capacitor of a conventional sample and hold device. The waveform 142 of the sample and hold device employing a current mirror to steer current into a sampling capacitor along an alternate path from a path through an input switch to the sampling capacitor illustrates an improvement in mitigating distortion of more than 20 DB over the conventional sample and hold device.

FIG. 8 illustrates a functional block diagram of a wireless receiver system 160 employing a sample and hold device in accordance with one aspect of the present invention. A transmission signal or burst is received by an antenna 162 , which captures the transmission signal and transmits the transmission signal to a front end processing component 164 . A transmission signal or burst can carry data, synchronization information, command information, calibration information or a variety of other information associated with the wireless system in which the wireless receiver is a member. The front end processing component 164 amplifies the transmission signal, converts the transmission signal to an intermediate frequency (IF) and filters the data signal to eliminate signals that are outside of the desired frequency band. It is to be appreciated that many variations in receiver front end processing exist. For example, some receiver front end processing includes utilizing multiple IF frequencies and successive frequency conversions. Additionally, some receivers provide direct radio frequency (RF) sampling without IF stages.

The front end processing component 164 feeds one or more analog-to-digital (A/D) converters 166 that sample the data signal and provide a digitized signal output. The one or more A/D converters include one or more sample and hold circuits 168 coupled to one or more converters 170 . The sample and hold circuits 168 employ a current mirror configuration as illustrated in FIGS. 2-4 to provide alternate current paths to sample switches provided in the sample and hold circuits 168 . A clock control component 172 controls the sample and hold phases of the sample and hold circuits in addition to the timing of the conversion processes executed by the converters 170 .

The digitized signal output of the one or more A/D converters 166 is then provided to a digital processor 174 . The digital processor 174 provides additional filtering of the digitized signals. The exact implementation of the digital processor 174 can vary depending on the particular receiver architecture being employed to provide the information in the transmission. The information can then be demodulated and/or decoded. The digital processor 174 receives digitized data associated with multiple samples of the input signal at varying amplitude levels. The digital processor can then perform a piecewise approximation to provide a digital representation as data output associated with the received input signal.

In view of the foregoing structural and functional features described above, methodologies in accordance with various aspects of the present invention will be better appreciated with reference to FIG. 9 . While, for purposes of simplicity of explanation, the methodology of FIG. 9 is shown and described as executing serially, it is to be understood and appreciated that the present invention is not limited by the illustrated order, as some aspects could, in accordance with the present invention, occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect the present invention.

FIG. 9 illustrates one particular methodology for operating a sample and hold device having a sampling capacitor having a first end coupled to an input voltage signal through an input sample switch and a second end to ground through a ground sample switch. The methodology begins at 200 where a continuous time-varying amplitude input signal V IN (e.g., AC sine wave) is applied at an input terminal of the sample and hold device. At 210 , the sample switches are opened and the hold switch is closed. At 220 , a first input current is replicated along a first alternate path relative to the path of the sampling capacitor. The first input current mirrors the input current drawn by the sampling capacitor. At 230 , a second input current is replicated along a second alternate path relative to the path of the sampling capacitor and the first alternate path. The second input current also mirrors the input current drawn by the sampling capacitor. The first and second input currents can be replicated concurrently. The methodology then proceeds to 240 .

At 240 , the first input current is steered to the input side of the capacitor after the input sample switch. The second input current is then steered out of the ground side of the capacitor before the ground sample switch at 250 . The first input current is provided at the input side of the capacitor and the second input current is removed from the ground side of the sampling capacitor concurrently. At 260 , the sample switches are opened and the hold switch is closed, so that the input signal charged on the sampling capacitor can be processed. The methodology then proceeds to 270 to determine if the sampling of the input signal has been completed. If the sampling of the input signal has not been completed (NO), the methodology returns to 210 to continue the sampling of the input signal. If the sampling of the input signal has been completed (YES), the methodology exits the routine at 280 and the complete sampling of the signal can then be converted into a digital representation of the input signal.

What has been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.