Column repair circuit in ferroelectric memory

The present invention claims the benefit of the Korean Patent Application No. P2001-58279 filed in Korea on Sep. 20, 2001, which is hereby incorporated by reference.

1. Field of the Invention

The present invention relates to a non-volatile ferroelectric memory, and more particularly, to a column repair circuit in a non-volatile ferroelectric memory having column redundancy.

2. Background of the Related Art

In general, a nonvolatile ferroelectric memory device such as a ferroelectric random access memory (FRAM), for example, has a data processing speed equivalent to that of dynamic random access memory (DRAM), and the nonvolatile ferroelectric memory device retains data during a power OFF state.

The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having high residual polarization characteristics. The residual polarization characteristics permit the retention of data when an applied electric field is removed.

FIG. 1 illustrates a characteristic curve of a hysteresis loop of a ferroelectric material according to the related art. In FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). The ‘d’ and ‘a’ states correspond to ‘1’ and ‘0’, respectively.

FIG. 2 illustrates a unit cell of a non-volatile ferroelectric memory according to the related art. In FIG. 2, the unit cell is provided with a bitline B/L formed along one direction, a wordline W/L formed perpendicular to the bitline, a plateline P/L formed spaced from the wordline along a direction identical to the wordline, a transistor T 1 having a gate connected to the wordline and a source connected to the bitline B/L, and a ferroelectric capacitor FC 1 having a first terminal connected to a drain of the transistor T 1 and a second terminal connected to the plateline P/L.

The data input/output operation of the related art non-volatile ferroelectric memory will be explained. FIG. 3A illustrates a timing diagram of a write mode operation of a ferroelectric memory according to the related art, and FIG. 3B illustrates a timing diagram of a read mode operation of the non-volatile ferroelectric memory.

During a writing mode, an external chip enable signal CSBpad transits from a ‘high’ level to a ‘low’ level and, at the same time, an external write enable signal WEBpad transits from a ‘high’ level to a ‘low’ level. When address decoding is started in the write mode, a pulse applied to the wordline transits from a ‘low’ level to a ‘high’ level to select a specific cell. Accordingly, the wordline is held at a ‘high’ level, the plateline has a ‘high’ level signal applied thereto for one period and a ‘low’ level signal applied thereto for another period in sequence. In order to write a logical value ‘1’ or ‘0’ to the selected cell, a ‘high’ or ‘low’ level signal synchronized to the write enable signal WEBpad is applied to the bitline. Moreover, if a ‘high’ level signal is applied to the bitline and a signal applied to the plateline is at a ‘low’ level in a period, then a signal applied to the wordline is at a ‘high’ level state, thereby a logical value ‘1’ is written to the ferroelectric capacitor. If a ‘low’ level signal is applied to the bitline, and a signal applied to the plateline is at a ‘high’ level, then a logical value ‘0’ is written to the ferroelectric capacitor.

The operation for reading the data stored in the cell by the foregoing write mode operation will be explained.

If the chip enable signal CSBpad is transited from a ‘high’ level to a ‘low’ level from outside of the cell, all bitlines are equalized to a ‘low’ level voltage by an equalizer signal before the wordline is selected. Then, after the bitlines are disabled, an address is decoded, and the decoded address transits the wordline from a ‘low’ level to a ‘high’ level, to select the cell. A ‘high’ level signal is applied to the plateline of the selected cell to break a data corresponding to a logical value ‘1’ stored in the ferroelectric memory. If a logical value ‘0’ is stored in the ferroelectric memory, then a data corresponding to the logical value ‘0’ is not broken. The data not broken, and the data broken thus provide values different from each other according to the aforementioned hysteresis loop, so that the sense amplifier senses a logical value ‘1’ or ‘0’. That is, when the data broken is a case when the value is changed from ‘d’ to ‘f’ in the hysteresis loop in FIG. 1, and the case of the data not broken is a case when the value is changed from ‘a’ to ‘f’ in the hysteresis loop in FIG. 1 . Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case of the data broken, a logical value ‘1’ is provided as amplified, and in the case of the data not broken, a logical value ‘0’ is provided as amplified. After the sense amplifier amplifies and provides the data, since an original data should be restored, the plateline is disabled from a ‘high’ level to a ‘low’ level during a state in which a ‘high’ level signal is applied to the wordline.

FIG. 4 illustrates a block diagram of a non-volatile ferroelectric memory according to the related art. In FIG. 4, the non-volatile ferroelectric memory is provided with a main cell array part 41 having a lower part allocated for a reference cell array part 42 , a wordline driver part 43 on one side of the main cell array part 41 for applying a driving signal to the main cell array part 41 and the reference cell array part 42 , and a sense amplifier part 44 under the main cell array part 41 . The wordline driver part 43 provides a driving signal to a main wordline in the main cell array part 41 , and a reference wordline in the reference cell array part 42 . The sense amplifier part 44 has a plurality of sense amplifiers each for amplifying a signal received from the bitline or the bitbarline.

The operation of the non-volatile ferroelectric memory will be explained, with reference to FIG. 5 . FIG. 5 illustrates a detail of FIG. 4, wherein the main cell array has a folded bitline structure like a DRAM. In FIG. 5, the reference cell array part 42 has a folded bitline structure, and a reference cell wordline and a reference cell plateline formed in a pair. The reference cell wordline and the reference cell plateline pairs are defined as RWL_ 1 /RPL_ 1 , and RWL_ 2 /RPL_ 2 . When a main cell wordline MWL_N−1 and a main cell plateline MPL_N−1 are enabled, the reference cell wordline RWL_ 1 and the reference cell plateline RPL_ 1 are enabled, to load a main cell data on the bitline, and a reference cell data on the bitbarline BB/L. When a main cell wordline MWL_N and a main cell plateline MPL_N are enabled, the reference cell wordline RWL_ 2 and the reference cell plateline RPL_ 2 are enabled, to load a main cell data on the bitbarline BB/L, and a reference cell data on the bitline B/L. A bitline voltage REF from the reference cell is between B H (High) and B L (Low), both are bitline voltages from the main cell. Therefore, in order to have the reference voltage REF to be between B_H and B_L, the reference cell may be operated by either of two methods.

A first method is storing a logical “1” in a capacitor in the reference cell by forming a size of the reference cell capacitor to be smaller than a size of a main cell capacitor. A second method is storing a logical “0” in a capacitor in the reference cell by forming a size of the reference cell capacitor to be greater than a size of a main cell capacitor. Thus, the non-volatile ferroelectric memory provides the reference voltage the sense amplifier requires 44 by using the two methods.

FIG. 6 illustrates a sense amplifier according to the related art included in the sense amplifier part in FIG. 4 . In FIG. 6, the sense amplifier is an inverter of a latch type, inclusive of two PMOS transistors, and two NMOS transistors. A first PMOS transistor MP 1 and a second PMOS transistor MP 2 are arranged opposite to each other, with an output terminal of the first PMOS transistor connected to a gate of the second PMOS transistor MP 2 , and an output terminal of the second PMOS transistor MP 2 connected to a gate of the first PMOS transistor MP 1 . Input terminals of the first, and second PMOS transistors MP 1 and MP 2 have a SAP signal applied thereto in common. The SAP signal is an enable signal for enabling the first, and second PMOS transistors MP 1 and MP 2 . An output terminal of the first PMOS transistor MP 1 is connected to the first NMOS transistor MN 1 in series, and an output terminal of the second PMOS transistor MP 2 is connected to the second NMOS transistor MN 2 in series. An output terminal of the second NMOS transistor MN 2 is connected to a gate of the first NMOS transistor MN 1 , and an output terminal of the first NMOS transistor MN 1 is connected to a gate of the second NMOS transistor MN 2 . The input terminals of the first and second NMOS transistors MN 1 and MN 2 have an SAN signal applied thereto in common. The SAN signal is a signal for enabling the first or second NMOS transistor MN 1 or MN 2 . Output terminals of the first PMOS transistor MP 1 and the first NMOS transistor MN 1 are connected to the bitline B_N in common, and output terminals of the second PMOS transistor MP 2 and the second NMOS transistor MN 2 are connected to a next bitline B_N+1. Thus, the sense amplifier with outputs connected to the bitlines B_N, and B_N+1 input/output to/from the main cell and the reference cell. Therefore, during a precharge period when the sense amplifier is disabled, all the SAP, SAN, B_N, and B_N+1 signals are in ½ Vcc states. Opposite to this, when the sense amplifier is enabled, the SAP signal is pulled-up to a high level, and the SAN signal is pulled-down to a ground voltage level.

However, the non-volatile ferroelectric memory has the following problems. First, provision of a repair circuit for each memory cell requires a large area of the repair circuits. Second, the large repair circuit area is not suitable for high density device packing. Third, structure, and algorithm of the repair circuit are complicated, and the repairing operation delays operation.

Accordingly, the present invention is directed to a column repair circuit in a non-volatile ferroelectric memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a column repair circuit in a non-volatile ferroelectric memory, which is favorable for high density device packing.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a column repair circuit in a non-volatile ferroelectric memory having main columns and redundancy columns includes a data input/output buffer part for data input/output between the non-volatile ferroelectric memory and an external circuit, a failed column coding part for controlling the main columns and the redundancy columns and connected in response to a failed column address signal to one of main input/output lines in the input/output buffer part and redundancy input/output lines, a repair column adjusting circuit part connected to the failed column coding part for providing a redundancy mode control signal, a data bus amplifying part for amplifying data between the main input/output lines and the main columns to control read/write operation, and a redundancy data bus amplifying part for amplifying data between the redundancy input/output lines and the redundancy columns in response to the redundancy mode control signal.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material according to the related art;

FIG. 2 illustrates a unit cell of a non-volatile ferroelectric memory according to the related art;

FIG. 3A illustrates a timing diagram of a write mode operation of a non-volatile ferroelectric memory according to the related art;

FIG. 3B illustrates a timing diagram of a read mode operation of a non-volatile ferroelectric memory according to the related art;

FIG. 4 illustrates a block diagram of a non-volatile ferroelectric memory according to the related art;

FIG. 5 illustrates a main cell array part of FIG. 4 according to the related art;

FIG. 6 illustrates a sense amplifier included in the sense amplifier part in FIG. 4 according to the related art;

FIG. 7 schematically illustrates an exemplary column repair circuit in a non-volatile ferroelectric memory in accordance with the present invention;

FIG. 8 illustrates an exemplary fail column address fuse box according to the present invention;

FIG. 9 illustrates an exemplary timing diagram during operation of a fail column address fuse box according to the present invention;

FIG. 10 illustrates an exemplary timing diagram when no repair is performed according to the present invention;

FIG. 11 illustrates an exemplary timing diagram when repair is performed according to the present invention;

FIG. 12 illustrates a detail of a fail input/output coding fuse box according to the present invention;

FIG. 13 illustrates a portion of a repair column adjusting circuit according to the present invention;

FIG. 14A illustrates a portion of a data bus amplifying block according to the present invention;

FIG. 14B illustrates a portion of a redundancy data bus amplifying block according to the present invention;

FIG. 15 illustrates an exemplary timing diagram when no repair operation is performed according to the present invention; and,

FIG. 16 illustrates a timing diagram when repair operation is performed according to the present invention.

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Systems of 256M — 2T2C, and 256M — 1T1C FeRAM cells will be explained before starting explanation of the present invention. The 256M — 2T2C FeRAM has four main cells in a top part thereof, and four reference cells in a bottom part thereof. On the other hand, the 256M — 1T1C FeRAM has two main cells in a top part thereof, and two reference cells in a bottom part thereof. Each of the main cells has 512 wordlines WL, 128 bitlines perpendicular to the wordline WL, and two redundancy bitlines. The bitlines, and the redundancy bitlines are connected to a data bus, and a redundancy data bus through particular y-decoders selected by column addresses, respectively.

FIG. 7 schematically illustrates a column repair circuit in a non-volatile ferroelectric memory in accordance with the present invention. In FIG. 7, the column repair circuit may include a data bus amplifying part 70 , a redundancy data bus amplifying part 71 , a fail column coding part 72 , a repair column adjusting circuit part 73 , and a data input/output buffer part 74 .

The data bus amplifying part 70 may include a plurality of data bus amplifying blocks 70 a , 70 b , . . . , 70 n , each for sensing and amplifying signals exchanged between input/output lines IO of the data input/output buffer part 74 and the data bus lines. The redundancy data bus amplifying part 71 may include a plurality of redundancy data bus amplifying blocks 71 a , 71 b , . . . , 71 m , each for sensing and amplifying signals exchanged between fail column address input/output lines IO and redundancy data bus lines. The fail column coding part 72 may include a plurality of fail column coding fuse blocks 72 a , . . . , 72 n . An i th fail column coding fuse block 72 may include a fail column address fuse box 72 i - 1 , and a fail input/output coding fuse box 72 i - 2 . The fail column address fuse box 72 i - 1 may provide a fail column address enable signal REDY upon reception of an address of a failed column. The fail input/output coding fuse box 72 i - 2 may form a pair with the fail column address fuse box 72 i - 1 to selectively connect the input/output lines IO in the data input/output buffer part 74 to main input/output lines MIO connected to the data bus amplifying part 70 , or to redundancy input/output lines RIO connected to the redundancy data bus amplifying part 71 in response to the fail column address enabling signal REDY from the fail column address coding fuse box 72 i - 1 .

The repair column adjusting circuit part 73 may receive the fail column address enabling signal REDY from each fail column address fuse box, and connect the input/output lines MIO of the data bus amplifying part 70 to the input/output lines IO of the data input/output buffer part 74 when no failed column exists. The repair column adjusting circuit part 73 may provide a redundancy mode control signal Redwlrhc for enabling the redundancy data bus amplifying block of the redundancy data bus amplifying part 71 when a failed column is detected.

A system of the fail column address fuse box 72 a - 1 will be explained, with reference to FIG. 8 . In FIG. 8, the fail column address fuse box 72 a - 1 may include a repair enabling signal control part 81 , an address fuse cut coding block part 82 , an address providing part 83 , and an address sensing part 84 . The fail column address fuse box 72 a - 1 may include 19 fuses in total, wherein a fuse in the repair enabling signal control part 81 may include a master fuse MF for determining repair of a column having a failure occurred therein. The 18 fuses in the address fuse cut coding block part 82 may be selectively servered according to a received column address.

In detail, the repair enabling signal control part 81 may include a master fuse MF, an NMOS capacitor C, an inverter INV 1 , NMOS transistors N 1 , N 2 , and N 3 , and a PMOS transistor P 1 . The master fuse MF may have one end connected to a VDD, and a node 1 , the another end may be connected to one end of the NMOS capacitor C. The NMOS transistor N 1 may be connected between the node 1 and a ground terminal GND. The inverter INV 1 may invert a signal from the node 1 , provide the inverted signal to a node 2 and to a gate terminal of the NMOS transistor N 1 . The PMOS transistor P 1 , and the NMOS transistors N 2 , and N 3 may be connected in series between the VDD and the ground terminal GND, and gate terminals of the PMOS transistor P 1 , and the NMOS transistor N 2 may be connected to the gate terminal. The gate terminal of the NMOS transistor N 3 may have a redundancy control signal CRED applied thereto. The redundancy control signal CRED may disable the fail column address fuse box during standby. The repair enabling signal control part 81 may provide a signal denoting a repair operation through a node 3 between the PMOS transistor P 1 and the NMOS transistor N 2 .

The address fuse cut coding block part 82 may include a plurality of unit address fuse cut coding blocks each having one NMOS transistor and one fuse connected in series. The units of one NMOS transistor and one fuse connected in series are in pairs. Each NMOS transistor NM 3 , . . . , NM 118 , . . . , NMn may have an address selection signal y< 0 >, yb< 0 >, . . . , y< 3 >, yb< 3 >, . . . , y<n>, yb<n>, and z< 0 >, zb< 0 >, . . . z< 3 >, zb< 3 >, . . . z<n>, zb<n> applied thereto, with signals of opposite phases applied to the units in a pair, respectively. Ends of the NMOS transistors and fuses connected in series in one pair may be connected, respectively.

In more detail, the address fuse cut coding block part 82 may include a circuit block for determining a ‘y’ address of a failed column, and a circuit block for determining a ‘z’ address of the failed column. The circuit block for determining a ‘y’ address of a fail column may include connected in succession in pairs starting from the node 3 , which is an output terminal of the repair enabling signal control part 81 , fuses F 1 and F 2 , NMOS transistors NM 1 and NM 2 , NMOS transistors NM 3 and NM 4 , fuses F 3 and F 4 , fuses F 5 and F 6 , NMOS transistors NM 5 and NM 6 , NMOS transistors NM 7 and NM 8 , fuses F 7 and F 8 , fuses F 9 and F 10 , and NMOS transistors NM 9 and NM 10 . One ends of the NMOS transistors NM 9 and NM 10 may be connected to the node 4 in common, for providing a ‘y’ address of a column to be repaired.

The circuit block for determining a ‘z’ address of the failed column has a system similar to the circuit block for determining a ‘y’ address of the failed column, inclusive of eight NMOS transistors NM 11 to NM 118 , and eight fuses F 11 to F 18 , corresponding to z< 0 >, zb< 0 >, . . . , z< 3 >, zb< 3 >. One ends of the NMOS transistors NM 11 and NM 12 may be connected to the node 3 , and one ends of the NMOS transistors NM 17 , and NM 18 may be connected to node 5 , for providing a ‘z’ address of a column to be repaired.

The address providing part 83 may include PMOS transistors P 2 to P 6 . One end of the PMOS transistor P 2 may be connected to VDD, the PMOS transistor P 3 may be connected between another end of the PMOS transistor P 2 and the node 4 , and the PMOS transistor P 4 may be connected between the another end of the PMOS transistor P 2 and the node 5 . A gate terminal of the second PMOS transistor P 2 may be connected to the node 6 for having an inverted failed column address enabling signal REDY from the address sensing part 84 applied thereto, and gate terminals of the PMOS transistor P 3 and P 4 may have an RYPCGB signal applied thereto.

FIG. 9 illustrates an exemplary timing diagram during operation of a fail column address fuse box according to the present invention. In FIG. 9, the RYPCGB signal is at an “H” level regardless of repair during one cycle of column address, dropped to an “L” level for a short pulse when a new address cycle starts, and rises to the “H” level again. Accordingly, even if the failed column address enabling signal REDY is at a high level when a normal operation starts after a repair operation, a normal operation is possible because the RYPCGB signal turns ON the third, and fourth PMOS transistors P 3 , and P 4 , to place the nodes 4 , and 5 at a high level. The PMOS P 5 and PMOS P 6 are connected to the VDD terminal and a point between nodes 4 and 5 , respectively, and gate terminals thereof are connected to a ground terminal GND to remain in an ON state and to secure the “H” levels of the nodes 4 and 5 when the levels of the nodes 4 and 5 are not in an “H” level due to an influence from threshold voltages of the NMOS transistors that receive ‘y’ and ‘z’ addresses of the failed column when no repair is performed.

The address sensing part 84 may include a NOR gate NOR for subjecting signals on nodes 4 and 5 to logical sum and inversion, inverters INV 2 and INV 3 for delaying an output from the NOR gate NOR to provide the failed column address enabling signal REDY, and an inverter INV 4 for inverting the failed column address enabling signal REDY and for forwarding the inverted failed column address enabling signal REDY to a gate terminal of the PMOS transistor P 2 in the address providing part 83 . If no failed column address is provided from the failed column address fuse box, i.e., when no repair is performed, the master fuse MF may not be severed, as shown in FIG. 10 . Accordingly, when a chip enable signal CSBpad is enabled from a high level H to a low level L because the redundancy control signal CRED transits from a low level L to a high level H to start operation of the circuit, which transits the node 1 and node 2 to a high level H and a low level L, respectively, and node 3 is at a high level H by the low level L of the node 2 , thereby transiting the nodes 4 and 5 to a high level H, the failed column address enabling signal REDY is transited to a low level L.

FIG. 11 illustrates an exemplary timing diagram when repair is performed according to the present invention. In FIG. 11, the master fuse MF is severed, and the fuse connected to the NMOS transistor in the same pair with the NMOS transistor that receives a failed column address signal having an opposite phase. Then the fuse connected to the NMOS transistor that receives an address signal of no failure is severed, and the fuse of the NMOS transistor in the same pair with the above NMOS transistor having an opposite phase is not severed. For an example, it is assumed that there are failures at locations of y< 4 >, y< 3 >, y< 2 >, y< 1 >, y< 0 >, and z< 3 >, z< 2 >, z< 1 >, z< 0 >, whereby fuses for y< 4 >, y< 3 >, y< 2 >, y< 1 >, y< 0 > may not be severed, but fuses for yb< 4 >, yb< 3 >, yb< 2 >, yb< 1 >, yb< 0 > may be severed. With regard to ‘z’ addresses, in the same method as the ‘y’ addresses, fuses for z< 3 >, z< 2 >, z< 1 >, and z< 0 > should not be severed, but fuses for zb< 3 >, zb< 2 >, zb< 1 >, and zb< 0 > should be severed.

Accordingly, if a circuit operation is enabled as the redundancy control signal CED is held at a high level H while the chip enable signal CSBpad is held at a low level L, then nodes 1 and 2 are held at a low level L, and a high level H respectively. Moreover, the node 3 transits to a low level L by the high level H of the node 2 , thereby making the nodes 3 , 4 , and 5 conductive to one another by the failed address that, in turn, makes the nodes 4 and 5 to be at a low level L. The low level L values of the nodes 4 and 5 transit the failed column address enabling signal REDY to a high level H. The fail column address enabling signal REDY from the fail column address fuse box is provided to the input/output coding fuse box corresponding to the failed column address fuse box, and the repair column adjusting circuit part 73 .

FIG. 12 illustrates a detail of a fail input/output coding fuse box according to the present invention. In FIG. 12, the fail input/output coding fuse box includes NMOS transistors NS 1 to NS 16 , and corresponding fuses FS 1 to FS 16 . Gate terminals of the NMOS transistors NS 1 to NS 16 have the fail column address enabling signal REDY applied thereto. The NMOS transistors NS 1 to NS 8 have one end connected to input/output lines IO of the data input/output buffer part 74 respectively, and another end connected to the main input/output lines MIO connected to the data bus amplifying blocks 70 a , 70 b , . . . , 70 n , respectively, through the fuses FS 1 to FS 8 . On the other hand, the NMOS transistors NS 9 to NS 16 have one end connected to input/output lines IO of the data input/output buffer part 74 , respectively, and another ends connected to the redundancy input/output lines RIO connected to the redundancy data bus amplifying blocks enabled through the fuses FS 9 to FS 16 .

FS 1 , NS 1 , NS 9 , and FS 9 are connected in series with an IO< 0 > provided between NS 1 and NS 9 and correspond to MIO< 0 >. Likewise, FS 2 , NS 2 , NS 10 , and FS 10 are interconnected with an IO< 1 > and correspond to MIO< 1 >; FS 3 , NS 3 , NS 11 , and FS 11 are interconnected with an IO< 2 > and correspond to MIO< 2 >; FS 4 , NS 4 , NS 12 , and FS 12 are interconnected with an IO< 3 > and correspond to MIO< 3 >; FS 5 , NS 5 , NS 13 , and FS 13 are interconnected with IO< 4 > and correspond to MIO< 4 >; FS 6 , NS 6 , NS 14 , and FS 14 are interconnected with an IO< 5 > and correspond to MIO< 5 >; FS 7 , NS 7 , NS 15 , and FS 15 are interconnected with an IO< 6 > and correspond to MIO< 6 >; and FS 8 , NS 8 , NS 16 , and FS 16 are interconnected with an IO< 7 > and correspond to MIO< 7 >, which are all connected in series between the redundancy input/output line RIO and corresponding main input/output lines MIO< 0 > to MIO< 7 >.

In the fail input/output coding fuse box, when the failed column address enabling signal REDY is an “H” level, the NMOS transistors NS 1 to NS 16 are turned ON, and only one of the fuses in series is severed. For example, if FS 1 is severed, FS 9 is not severed, connecting an input/output line IO< 0 > of the data input/output buffer part 74 to the redundancy input/output line RIO.

FIG. 13 illustrates a detailed portion of a repair column adjusting circuit part 73 (in FIG. 7 ). In FIG. 13, the repair column adjusting circuit part 73 may include NOR gates NOR 1 to NOR 8 , an NAND gate NAND, inverters INV 11 to INV 15 , and NMOS transistors NM 20 to NM 27 . Each of the NOR gates NOR 1 to NOR 4 may include two failed column address enabling signals REDY applied thereto from a failed column coding fuse block in the failed column coding part 72 in succession. Moreover, the NOR gate NOR 1 receives REDY< 0 > and REDY< 1 >; the NOR gate NOR 2 receives REDY< 2 > and REDY< 3 >; the NOR gate NOR 3 receives REDY< 4 > and REDY< 5 >; and the NOR gate NOR 4 receives REDY< 6 > and REDY< 7 >, and are subject to logical sum, and inversion, and forward operations.

The NOR gates NOR 5 to NOR 8 subject output signals of the NOR gates NOR 1 to NOR 4 and a mode control signal wlrhc to logical sum, and inversion operations. Moreover, the NOR gate NOR 5 subjects an output signal of the NOR gate NOR 1 and the mode control signal wlrhc to logical sum, and inversion operations, and the NOR gates NOR 6 to NOR 8 are also subject outputs of the NOR gates NOR 2 to NOR 4 and the mode control signal wlrhc to a logical sum operation.

The inverters INV 11 to INV 14 invert output signals of the NOR gates NOR 5 to NOR 8 , respectively, to provide redundancy mode control signals Redwlrhc for controlling read/write operation of the redundancy data bus amplifying blocks in the redundancy data bus amplifying part 71 . The NAND gate NAND subjects output signals of the NOR gates NOR 1 to NOR 4 to logical sum and inversion operations. The inverter INV 15 inverts an output signal of the NAND gate NAND, and provides the output signal of the NAND gate NAND to a node 7 , and to gates of the NMOS transistors NM 20 to NM 27 . The NMOS transistors NM 20 to NM 27 have one end connected the main input/output lines MIO connected to the data bus amplifying part 70 , and another end connected to the input/output lines IO of the data input/output buffer part 74 .

When no repair is performed, since the failed column address enabling signals REDY transit to low level L states, the redundancy mode control signal Redwlrhc, and a node 7 signal transits to a high H state. Thus, the NMOS transistors NM 20 to NM 27 are turned ON, and connect the main input/output line MIO with the input/output line IO of the data input/output buffer part 74 (in FIG. 7 ). Accordingly, a signal from the data input/output buffer part 74 is transmitted to a memory cell through the input/output line IO of the data input buffer part and the main input/output line MIO in a write mode, and a data from the memory cell to the data input/output buffer part 74 through the main input/output line MIO and the input/output line IO of the data input/output buffer part in a reading mode.

In FIG. 7, the data bus amplifying part 70 may include a plurality of data bus amplifying blocks 70 a to 70 n , each for regular data input/output. The redundancy data bus amplifying part 71 may include a plurality of redundancy data bus amplifying blocks 71 a to 71 m , for using one of the redundancy data bus amplifying blocks in the redundancy data bus amplifying part 71 instead of the data bus amplifying block of a failed column when a column fail occurs.

FIG. 14A illustrates a portion of a data bus amplifying block according to the present invention. In FIG. 14A, each of the data bus blocks in the data bus amplifying part 70 (in FIG. 7) uses an equalizing control signal DBEQB, a latch enable control signal DBLCH, an amplification enabling signal DBSEN, and a mode control signal wlrhc for making smooth data transfer between the main input/output lines MIO and the data bus lines DBTOP or DBBOT connected to top or bottom cell arrays.

FIG. 14B illustrates a portion of a redundancy data bus amplifying block according to the present invention. In FIG. 14B, the redundancy data bus amplifying block uses a circuit identical to the data bus amplifying block, and uses the equalizing control signal DBEQB, the latch enable control signal DBLCH, and the amplification enabling signal DBSEN as control signals for making smooth data transfer between the redundancy input/output lines RIO, or the top and bottom data bus lines DBTOP and DBBOT. Moreover, the redundancy data bus amplifying block uses control signals almost identical to the data bus amplifying block, except that, different from the data bus amplifying block, the redundancy data bus amplifying block uses the redundancy mode control signal Redwlrhc from the column redundancy adjusting circuit part 73 (in FIG. 7) instead of the mode control signal wlrhc. Since the data bus amplifying block in FIG. 14 A and the redundancy data bus amplifying block in FIG. 14B have the same system, for convenience of explanation, only the redundancy data bus amplifying block will be explained.

The redundancy data bus amplifying block uses the equalizing control signal DBEQB, the latch enable control signal DBLCH, the amplification enabling signal DBSEN, and the redundant mode control signal Redwlrhc as control signals, for receiving/forwarding the data bus signal DBTOP connected to the redundancy input/output line RIO and the top cell, and the data bus signal DBBOT connected to the bottom cell. Moreover, the redundancy data bus amplifying block includes an equalize/precharge control part 14 b - 1 , a data bus amplifying circuit part 14 b - 2 , a read mode control part 14 b - 3 , a mode control signal receiving part 14 b - 4 , and a write mode control part 14 b - 5 .

The equalize/precharge control part 14 b - 1 includes a PMOS transistor P 21 having one end connected to VDD, another end connected to a data bus DBTOP of a top cell, and a gate terminal having the equalizing control signal DBEQB applied thereto; a PMOS transistor P 22 having one end connected to VDD, another end connected to a data bus DBBOT of the bottom cell, and a gate terminal having the equalizing control signal DBEQB applied thereto; and a PMOS transistor P 23 having one end connected to the data bus DBTOP of the top cell, and another end connected to the data bus DBBOT of the bottom cell for equalizing the data bus DBTOP of the top cell, and the data bus DBBOT of the bottom cell according to the equalizing control signal DBEQB applied to a gate terminal thereof.

The data bus amplifying circuit part 14 b - 2 includes a PMOS transistor P 24 having one end connected to VDD and another end connected to a node 8 ; a PMOS transistor P 25 having one end connected to VDD, another end connected to the node 9 , and a gate terminal connected to the node 8 ; and a PMOS transistor P 26 having one end connected to the node 8 and another end connected to the node 9 for equalizing the nodes 8 and 9 according to the equalizing control signal applied to a gate terminal thereof. A gate terminal of the PMOS transistor P 24 is connected to the node 9 . The data bus amplifying circuit part 14 b - 2 also includes NMOS N 21 and N 22 connected in series between the nodes 8 and 9 , having gate terminals connected to the data bus DBTOP of the top cell, and the data bus DBBOT of the bottom cell respectively, and an NMOS transistor N 23 connected between a node 10 , a terminal connecting the NMOS transistor N 21 and the NMOS transistor N 22 , and a ground terminal GND, and having a gate terminal for receiving the amplification enabling signal DBSEN.

The read mode control part 14 b - 3 includes an inverter INV 21 for inverting the latch enable control signal DBLCH, transfer gates TS 1 and TS 2 that are enabled according to the latch enable control signal DBLCH and an output of the inverter INV 21 , and connecting the nodes 8 and 9 to the data bus DBTOP of the top cell, and the data bus DBBOT of the bottom cell respectively; a NAND gate NAND 11 for subjecting the latch enable control signal DBLCH and the redundancy mode control signal Redwlrhc to logical production and inversion, an inverter INV 22 for inverting an output of the NAND gate NAND 11 ; and a transfer gate TS 3 for connecting a redundancy input/output line connected to the redundancy data bus amplifying block enabled in response to an output signals of the inverter INV 22 and the NAND gate NAND 11 and the data bus DBTOP of the top cell.

The mode control signal receiving part 14 b - 4 includes an inverter INV 23 for inverting the redundancy mode control signal Redwlrhc, a NAND gate NAND 12 for subjecting an output signal of the inverter INV 23 , and a signal on the redundancy input/output line RIO to logical production and inversion; a PMOS transistor P 27 having one end connected to VDD, another end connected to the redundancy input/output line RIO, and a gate terminal with an output signal of the NAND gate NAND 12 applied thereto; and an inverter INV 24 for inverting an output signal of the inverter INV 23 .

The write mode control part 14 b - 5 includes transfer gates TS 4 and TS 5 each to be enabled in response to an output signal of the inverter INV 23 or INV 24 for connecting one end to either node 8 or 9 to another end; an inverter INV 25 for inverting a signal from the other end of the transfer gate TS 5 , and for providing to the other end of the transfer gate TS 4 and a transfer gate TS 7 ; and a transfer gate TS 7 for being enabled in response to an output signals of the inverter INV 23 , and the inverter INV 24 , to connect the redundancy input/output terminal RIO connected to one end thereof to the other end, and an output of the inverter INV 25 applied to one end thereof to the other end, respectively.

The transfer gate TS 1 , and the transfer gate TS 2 are enabled/disabled in response to the latch enable control signal DBLCH, and an output signal of the inverter INV 21 on the same time, and the transfer gates TS 4 , TS 5 , and TS 6 are enabled/disabled in response to output signals of the inverters INV 23 and INV 24 at the same time. On the other hand, the transfer gate TS 7 is enabled in a case the transfer gates TS 4 , TS 5 , and TS 6 are disabled, and disabled in a case the transfer gates TS 4 , TS 5 , and TS 6 are enabled.

As has been explained, the redundancy data bus amplifying part 71 includes a plurality of, for an example, ‘m’ redundancy data bus amplifying blocks 71 a to 71 m having the same system for receiving redundancy mode control signals Redwlrhc< 0 >, Redwlrhc< 1 >, Redwlrhc< 3 >, . . . , Redwlrhc<m>, to amplify signals of the redundancy data buses, respectively.

FIGS. 15, and 16 illustrate exemplary control signals used for making smooth transfer of data between the main input/output lines MIO, or redundancy input/output lines RIO, and data buses DBTOP of a top cell, and data buses DBBOT of the bottom cell, and timing diagram of the control signals. In FIG. 15, when no repair is performed, the failed column address enabling signal REDY is at a low level L, and the redundant enabling signal Redwlrhc signal is held at a high level H by the low L value of the failed column address enabling signal REDY. According to this, the node 7 transits to a high level H, leading an input data to the data bus amplifying block through the input/output terminals IO connected to the data input/output buffer part 74 , and the main input/output terminals MIO in writing, and leading a data provided to the top, and bottom cell data buses DBTOP, and DBBOT to the main input/output terminals MIO and the input/output terminals IO of the data input/output buffer part 74 , and therefrom to the data input/output buffer part 74 .

On the other hand, when a repair is performed, for an example, when a defect is detected at IO< 0 > as shown in FIG. 16, the REDY< 0 > transits to a high level H, and the REDY< 1 - 7 > transits to a low level L. In the repair column adjusting circuit part 73 , the Redwlrhc< 0 > transits to a low level L, the Redwlrhc< 1 - 3 > is held at a high level H, and the node 7 transits to a low level L in response to the high level H of the REDY< 0 >, and the low level L of the REDY< 1 >. In the fail input/output coding fuse box 72 i - 2 , the fuse FS 1 is severed, and the fuse FS 9 is not severed, to disconnect the IO< 0 > from MIO< 0 >, and connect the IO< 0 > to RIO. Accordingly, the redundancy input/output line RIO connected to the IO< 0 > is connected to one selected from the four redundancy data bus amplifying blocks in the redundancy data bus amplifying part 70 . Thus, by means of the rest seven data bus amplifying blocks excluding the data bus amplifying block connected to the IO< 0 > having the defect occurred therein, and the redundancy data bus amplifying block, ×8 data input/output is made possible.

As has been explained, the column repair circuit in a non-volatile ferroelectric memory has the following advantages. First, the provision of a repair circuit, not for every memory cell, but one repair circuit for all memory cells reduces an area occupied by the repair circuit, that improves the device packing density. Second, the application of a repair algorithm to all memory cells at a time improves an efficiency of a repair operation, and permits to shorten a fuse cutting time period in the repairing.

It will be apparent to those skilled in the art that various modifications and variations can be made in the column repair circuit in a non-volatile ferroelectric memory of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.