Method for implanting ions in a semiconductor

The present disclosure generally relates to the manufacturing of semiconductors and more particularly relates to a method of implanting ions in a semiconductor.

As the dimensions of semiconductor devices scale down, adverse short channel effects become significant. One way to reduce short channel effects is by the creation and activation of a well confined band of dopants disposed within the semiconductor device. However, the efficient creation and activation of such a well confined band is problematic due to a number of factors including the diffusivity and activation characteristics of the implanted dopants. Accordingly a method of implanting ions in a semiconductor to help reduce short channel effects is desired.

In accordance with one illustrative embodiment, a method of implanting ions in a silicon substrate is provided. The method includes advancing indium ions into the silicon substrate for a first time period. The method also includes advancing boron ions into the silicon substrate for a second time period. The time period for advancement of the indium ions is initiated prior to the time period for advancement of the boron ions.

In accordance with another illustrative embodiment, a method of disposing indium ions and boron ions below a surface of a semiconductor is provided. The method includes applying a mask structure adjacent to the semiconductor substrate. The mask structure includes an opening defined therein. Additionally, the method includes initiating the advancement of indium ions through the opening of the mask structure and into the semiconductor substrate. The method also includes advancing the boron ions through the opening of the mask structure and into the semiconductor substrate. The advancement of the indium ions is initiated prior to the advancement of the boron ions.

In accordance with still another illustrative embodiment, a method of fabricating a semiconductor device is provided. The method includes implanting indium ions into a substrate of a semiconductor material of the semiconductor device for a first time period. The method also includes implanting boron ions into the substrate for a second time period. The first time period is initiated prior to the second time period and the indium ions and the boron ions define a doped channel in the substrate.

FIG. 1 . is a cross sectional schematic representation of ions being implanted into a semiconductor substrate through an opening of a mask structure;

FIG. 2 . is a schematic representation of the semiconductor device of FIG. 1 positioned in an annealing chamber after implantation of ions therein so as to define a doped channel within the semiconductor substrate;

FIG. 3 . is a graphical representation of sheet resistivity of a silicon substrate after rapid thermal process (RTP) annealing in which (i) boron ion implantation into the silicon substrate was initiated prior to indium ion implantation, (ii) indium ions alone were implanted into the silicon substrate, and (iii) indium ion implantation into the silicon substrate was initiated prior to boron ion implantation; and

FIG. 4 . is a graphical representation of hole concentration versus silicon substrate depth where (i) indium ion implantation into the silicon substrate was initiated prior to boron ion implantation (▪) and (ii) boron ion implantation into the silicon substrate was initiated prior to indium ion implantation (□).

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.

Referring now to FIG. 1 , there is shown an implanter 22 , a flow of ions 20 , and a semiconductor device 10 . The semiconductor device 10 includes a surface 12 and a substrate 14 , for example silicon, germanium, or gallium compounds. A mask structure 16 having an opening 18 is applied adjacent to (e.g. in contact with) substrate 14 to improve control of the advancement of ions into substrate 14 . The mask structure may include a low temperature oxide, photo-resistive material, and/or other process blocking materials commonly known to one ordinarily skilled in the art.

In one illustrative embodiment, indium ions are advanced into substrate 14 for a first time period and boron ions are advanced into substrate 14 for a second time period. However, it should be understood that the advancement of the indium ions is initiated prior to the advancement of the boron ions. For example, indium ions are implanted in substrate 14 through opening 18 of mask structure 16 with implanter 22 . In particular, one way of implanting indium ions through opening 18 of mask structure 16 with implanter 22 is to dope substrate 14 with an ion dose of about 0.8×10 13 indium ions per square centimeter by ion implanter 22 utilizing about 90 KeV acceleration voltage, about 7 degrees tilt, and about 23 degrees twist. With respect to the implantation of the boron ions, substrate 14 is doped to an ion dose of about 5×10 12 boron ions per square centimeter by ion implanter 22 utilizing about 25 KeV acceleration voltage, about 7 degrees tilt, and about 23 degrees twist. Advancing indium and boron ions into substrate 14 in the above described manner results in an indium ion and boron ion doped channel 26 being formed into the region of substrate 14 through opening 18 of mask structure 16 as shown in FIG. 2 . It should be appreciated that a mask structure 16 can be applied adjacent to substrate 14 prior to the advancement of ions to control the dispersion of dopants within substrate 14 . It should also be appreciated that the advancement of the indium ions and boron ions can occur in an environment which is substantially free of oxygen.

While the above described illustrative embodiment sets forth that doped channel 26 is created within a region delineated by the opening of the mask structure, it should be appreciated that other methods of delineating a region for the control of ion dispersion may be used.

Referring now to FIG. 2 , there is schematically shown an annealing chamber 24 and semiconductor device 10 after being subjected to the above described method of implanting ions. In particular, semiconductor device 10 is positioned within annealing chamber 24 such that semiconductor device 10 can be subjected to, for example, an annealing process in a substantially oxygen free environment. It should be appreciated that the annealing process can include heating semiconductor device 10 for a period of time followed by cooling semiconductor device 10 for a period of time.

One way of annealing semiconductor device 10 in a substantially oxygen free environment is to conduct the annealing process in a nitrogen atmosphere. For example, the atmosphere contained within annealing chamber 24 can be a nitrogen atmosphere at a pressure of about 760 Torr to about 780 Torr. After placing semiconductor device 10 in annealing chamber 24 under a nitrogen atmosphere in the above described manner, semiconductor device 10 is heated to a temperature of about 550 degrees Celsius to about 1,000 degrees Celsius at a rate of about 35 degrees Celsius to about 75 degrees Celsius per second. Semiconductor device 10 is then maintained at about 550 degrees Celsius to about 1,000 degrees Celsius for about 10 seconds to about 30 seconds. Thereafter, semiconductor device 10 is cooled at a rate greater than 35 degrees Celsius per second. For example, a cooling rate of about 50 degrees Celsius per second to about 90 degrees Celsius per second can be utilized. In particular, a cooling rate of about 60 degrees Celsius per second to about 90 degrees per second can be employed. Illustratively, a cooling rate of about 80 degrees per second can be utilized. It should also be understood that helium can be advanced into annealing chamber 24 during the cooling process to support advanced rates of cooling. Annealing chamber 24 is then depressurized and semiconductor device 10 is removed from annealing chamber 24 for further processing. Illustratively, the above annealing process takes place subsequently to the advancement of indium and boron ions into substrate 14 . In particular, the above annealing process occurs subsequently to the advancement of indium and boron ions into substrate 14 and prior to any additional processing steps. In particular, the above annealing process can occur prior to the deposition of dopant diffusion, for example, the deposition of source and drain dopants into semiconductor device 10 .

Now referring to FIG. 3 , a graphical representation is shown of the resultant sheet resistivity of a doped channel created by one of three different ion implantation methods, i.e. (i) an implantation method which includes initiating the implantation of boron ions into a semiconductor substrate prior to initiating the implantation of indium ions into the semiconductor substrate (note that the data for the aforementioned method is indicated by a “Boron+Indium” label), (ii) an implantation method which includes the implantation of indium ions alone into a semiconductor substrate (note that the data for the aforementioned method is indicated by a “Indium” label), (iii) and an implantation method which includes initiating the implantation of indium ions into a semiconductor substrate prior to initiating the implantation of boron ions into the semiconductor substrate (note that the data for the aforementioned method is indicated by a “Indium+Boron” label). For each implantation procedure, two annealing processes are represented. The left bar associated with each of the above described labels (i.e. “Boron+Indium”, “Indium”, “Indium+Boron”) depicts an annealing process wherein a semiconductor device is heated to and then maintained at a temperature of about 1,000 degrees Celsius for a time period of about 30 seconds. The semiconductor device is then cooled in a manner consistent with that described above. The right bar associated with each of the above described labels depicts an annealing process wherein a semiconductor device is heated to and then maintained at a temperature of about 1,000 degrees Celsius for a time period of about 10 seconds. The semiconductor device is then cooled in a manner consistent with that described above. It should be appreciated that, generally, a lower doped channel sheet resistivity is desired and, along with an increased activation of dopants at the same ion dose, results in a higher drive current. As shown in FIG. 3 , the method of initiating the implantation of indium ions prior to initiating the implantation of boron ions results in a lower doped channel sheet resistivity for each annealing process which incorporates a 30 second maintenance time at about 1,000 degrees Celsius. In a similar fashion, FIG. 3 also shows that the method of initiating the implantation of indium ions prior to initiating the implantation of boron ions results in a lower doped channel sheet resistivity for each annealing process which incorporates a 10 second maintenance time at about 1,000 degrees Celsius.

Now referring to FIG. 4 , a graphical representation of the concentration of activated indium and boron dopants by dopant concentration depth in a semiconductor device subjected to the above described implantation method is shown. In particular, the curve represented by the symbol (▪) depicts the concentration of indium and boron dopants by dopant concentration depth resulting from initiating the implantation of indium ions prior to initiating the implantation of boron ions into the semiconductor substrate. In contrast, the curve represented by the symbol (□) depicts the concentration of indium and boron dopants by dopant concentration depth resulting from initiating the implantation of boron ions prior to initiating the implantation of indium ions into the semiconductor substrate. As shown in FIG. 4 , the method of initiating the implantation of indium ions prior to initiating the implantation of boron ions results in a higher concentration of holes (i.e. indium and boron ions) around the 0.05 micrometer depth. A high level of hole concentration at this depth is indicative of the formation of a steep retrograde doped channel and helps reduce the short channel effects associated with scaled downed semiconductor devices.

There are a plurality of advantages of the concepts of the present disclosure arising from the various features of the apparatus and methods described herein. It will be noted that alternative embodiments of the apparatus and methods of the present disclosure may not include all of the features described yet still benefit from at least some of the advantages of such features. Those of ordinary skill in the art may readily devise their own implementations of the apparatus and methods of the present disclosure that incorporate one or more of the features of the present disclosure and fall within the spirit and scope of the invention defined by the appended claims.