Inventor

Mohammad R. Mirabedini

Inventor

Redwood City, CA, US

Overview

2002–2011

Patent span

Electricity

Primary field (CPC H)

Patents· 15 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices48%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1035%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%

PatentTitleYear

8,021,955'Method characterizing materials for a trench isolation structure having low trench parasitic capacitance'2011 7,619,294'Shallow trench isolation structure with low trench parasitic capacitance'2009 7,429,749'Strained-silicon for CMOS device using amorphous silicon deposition or silicon epitaxial growth'2008 7,408,227'Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide'2008 7,262,119'Method for incorporating germanium into a semiconductor wafer'2007 7,148,131'Method for implanting ions in a semiconductor'2006 7,138,292'Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide'2006 7,129,516'Ion recoil implantation and enhanced carrier mobility in CMOS device'2006 7,001,823'Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance'2006 6,989,331'Hard mask removal'2006 6,982,229'Ion recoil implantation and enhanced carrier mobility in CMOS device'2006 6,930,362'Calcium doped polysilicon gate electrodes'2005 6,562,729'Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit'2003 6,544,829'Polysilicon gate salicidation'2003 6,436,845'Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2011Patents assigned to LSI LOGIC CORP (11)· patent assignee history

2002–2003Based in Daly City, CA, US· patent location history

2003–2011Based in Redwood City, CA, US· patent location history

2007–2009Patents assigned to LSI CORP (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
LSI LOGIC CORP	11	2002–2011
LSI CORP	4	2007–2009

Locations

Location	Patents	Span
Redwood City, California, US	13	2003–2011
Daly City, California, US	2	2002–2003