Semiconductor memory device

1. Field of the Invention

The present invention relates to a semiconductor memory device constituting the memory cell of a CMOS static RAM.

2. Description of Related Art

FIG. 9 is a layout configuration diagram showing a conventional semiconductor memory device.

Referring to FIG. 9 , reference numeral 1 denotes an one-bit SRAM, reference numerals N 1 , N 2 , N 3 , and N 4 denote NMOS transistors formed in a P well region, and reference numerals P 1 and P 2 denote PMOS transistors formed in a N well region. The NMOS transistor N 1 and PMOS transistor P 1 make up a first inverter, and the NMOS transistor N 2 and PMOS transistor P 2 make up a second inverter.

Reference numeral a 1 denotes a first metal wiring a 1 which connects the drain of NMOS transistor N 1 with that of PMOS transistor P 1 , reference numeral a 2 denotes a second metal wiring which connects the output terminal of the first inverter with the input terminal of the second inverter, and the first metal wiring a 1 and second metal wiring a 2 make up a memory node. Reference numeral b 1 denotes a first metal wiring b 1 which connects the drain of NMOS transistor N 2 with that of PMOS transistor P 2 , reference numeral b 2 denotes a second metal wiring which connects the output terminal of the second inverter with the input terminal of the first inverter, and the first metal wiring b 1 and second metal wiring b 2 make up a memory node.

Reference numeral C denotes a diffusion contact hole, reference numeral GC denotes a gate contact hole, reference numeral VDD denotes the power supply potential of a P+ diffused region formed in the N well region, reference numeral GND denotes the ground potential of a N+ diffused region formed in the P well region, reference numeral WL 1 denotes a word line connected with the gate of the NMOS transistor N 3 , reference numeral WL 2 denotes a word line connected with the gate of the NMOS transistor N 4 , reference numeral BL 1 denotes a bit line connected with the drain of the NMOS transistor N 3 , and reference numeral BL 2 denotes a bit line connected with the drain of the NMOS transistor N 4 .

The operation will next be described.

When parts are laid out as shown in FIG. 9 , a SRAM can be formed into the circuit configuration shown in FIG. 2 .

When a semiconductor memory device as shown in FIG. 9 is formed, for instance, the NMOS transistors N 1 , N 2 , N 3 , and N 4 , the PMOS transistors P 1 and P 2 , the first metal wirings a 1 and b 1 , and the word lines WL 1 and WL 2 are formed in the first layer. The second metal wirings b 1 and b 2 are formed in the second layer, and the bit lines BL 1 and BL 2 are formed in the third layer.

Such an arrangement of the conventional semiconductor memory device as mentioned above contributes to enhancement of the integration degree of the SRAM. However, this arrangement requires the second metal wirings a 2 and b 2 to be wired in a layer different from the first metal wirings a 1 and b 1 . For this reason, in proportion to the increase in the number of the wiring layers, manufacturing processes increase. As a result, this brings about long manufacturing terms and high manufacturing costs.

In addition to the above-described prior art, JP-A-28401/2001 discloses a technology in which the second metal wirings a 2 and b 2 are wired in the same layer as the first metal wirings a 1 and b 1 by dividing the P well region. However, in this case, because one word line is shared, the word line must be wired in a different layer.

The present invention has been made to solve the above-mentioned problems, and an object of thereof is to provide a semiconductor memory device in which high integration degree can be achieved by use of a small number of wiring layers.

In the semiconductor memory device according to the present invention a first PMOS transistor and a second PMOS transistor are formed in a N well region, a first NMOS transistor and a third NMOS transistor are formed in a first P well region, and a second NMOS transistor and a fourth NMOS transistor are formed in a second P well region, and a first word line is wired to the third NMOS transistor and a second word line is wired to the fourth NMOS transistor.

According to the present invention, since the semiconductor memory device is arranged such that the first PMOS transistor and the second PMOS transistor are formed in a N well region, the first NMOS transistor and the third NMOS transistor are formed in a first P well region, and the second NMOS transistor and the fourth NMOS transistor are formed in a second P well region, and that a first word line is wired to the third NMOS transistor, and a second word line is wired to the fourth NMOS transistor, high integration degree can be achieved by use of a small number of wiring layers.

In the semiconductor memory device according to the present invention the first to the fourth NMOS transistors are formed in a P well region, the first PMOS transistor is formed in a first N well region, and the second PMOS transistor is formed in a second N well region, and a first word line is wired to the third NMOS transistor and a second word line is wired to the fourth NMOS transistor.

According to the present invention, since the first to the fourth NMOS transistors are formed in a P well region, the first PMOS transistor is formed in a first N well region, and the second PMOS transistor is formed in a second N well region, and since a first word line is wired to the third NMOS transistor and a second word line is wired to the fourth NMOS transistor, high integration degree can be achieved by use of a small number of wiring layers.

FIG. 1 is a layout configuration diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing the semiconductor memory device shown in FIG. 1 .

FIG. 3 is a layout configuration diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing the semiconductor memory device shown in FIG. 3 .

FIG. 5 is a layout configuration diagram showing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing the semiconductor memory device shown in FIG. 5 .

FIG. 7 is a layout configuration diagram showing a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing the semiconductor memory device shown in FIG. 7 .

FIG. 9 is a layout configuration diagram showing a conventional semiconductor memory device.

The embodiments of the present invention will next be described in detail with reference to the attached drawings.

First Embodiment

FIG. 1 is a layout configuration diagram showing a semiconductor memory device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing the semiconductor memory device shown in FIG. 1 .

Referring to FIGS. 1 and 2 , reference numeral 1 denotes an one-bit SRAM, reference numeral N 1 denotes an NMOS transistor (a first NMOS transistor) formed in a first P well region, reference numeral N 2 denotes an NMOS transistor (a second NMOS transistor)formed in a second P well region, reference numeral N 3 denotes an NMOS transistor (a third NMOS transistor) formed in the first P well region. Reference numeral N 4 denotes an NMOS transistor (a fourth NMOS transistor) formed in the second P well region. Reference numeral P 1 denotes a PMOS transistor (a first PMOS transistor) formed in a N well region, and reference numeral P 2 denotes a PMOS transistor (a second PMOS transistor) formed in the N well region. The NMOS transistor N 1 and PMOS transistor P 1 make up a first inverter, and the NMOS transistor N 2 and PMOS transistor P 2 a second inverter.

Reference numeral a 1 denotes a first metal wiring which connects the drain of the NMOS transistor N 1 with the drain of the PMOS transistor P 1 , reference numeral a 3 denotes a first metal wiring which connects the output terminal of the first inverter with the input terminal of the second inverter, and the first metal wirings a 1 and a 3 make up a memory node. Reference numeral b 1 denotes a first metal wiring which connects the drain of the NMOS transistor N 2 with the drain of the PMOS transistor P 2 , reference numeral b 3 denotes a first metal wiring which connects the output terminal of the second inverter with the input terminal of the first inverter, and the first metal wirings b 1 and b 3 make up a memory node.

Reference numeral C denotes a diffusion contact hole, reference numeral GC denotes a gate contact hole, reference numeral VDD denotes the power supply potential of a P+ diffused region formed in the N well region, and reference numeral GND denotes the grand potential of a N+ diffused region formed in the P well region. Reference numeral WL 1 denotes a word line (a first word line) connected with the gate of NMOS transistor N 3 . Reference numeral WL 2 denotes a word line (a second word line) connected with the gate of the NMOS transistor N 4 . Reference numeral BL 1 denotes a bit line connected with the drain of the NMOS transistor N 3 , reference numeral BL 2 denotes a bit line connected with the drain of the NMOS transistor N 4 . Reference numeral PL 1 denotes a polysilicon wiring which connects the gate of the PMOS transistor P 1 with the gate of the NMOS transistor N 1 , reference numeral PL 2 denotes a polysilicon wiring which connects the gate of the PMOS transistor P 2 with the gate of NMOS transistor N 2 , a polysilicon wiring PL 3 makes up the word line WL 1 , and a polysilicon wiring PL 4 makes up the word line WL 2 .

The operation will next be described.

FIG. 1 shows layers extending from the well to the first metal wirings, in which one N-type well region and two P-type well regions are formed. The first and the second P well regions and the N well region are formed in a direction orthogonal to the word lines WL 1 and WL 2 in a strip-of-paper shape.

The PMOS transistors P 1 and P 2 are formed in one N well region, the NMOS transistors N 1 and N 3 in the first P well region, and the NMOS transistors N 2 and N 4 in the second P well region.

In FIG. 1 , the parts in which the diffused layer and the polysilicon layer being overlapped each other will be transistors. The gate of the PMOS transistor P 1 and the gate of the NMOS transistor N 1 are connected each other through the polysilicon wiring PL 1 , and the polysilicon wiring PL 1 is connected with the first metal wiring b 3 constituting a memory node. In a similar manner, the gate of the PMOS transistor P 2 and the gate of the NMOS transistor N 2 are connected each other through the polysilicon wiring PL 2 , and the polysilicon wiring PL 2 is connected with the first metal wiring a 3 constituting a memory node.

A P+ diffused region is formed by injecting a P-type impurity in the N well region, and a N+ diffused region is formed by injecting an N-type impurity in the P well region. In each of the diffused regions, at least one or more diffusion contact holes C are formed, and the diffused region is connected with the first metal wirings a 1 , a 3 , b 1 , and b 3 through the diffusion contact hole C.

The N+ diffused region located in the center of the first P well region and the P+ diffused region located in the upper of the N well region are electrically connected through the diffusion contact hole C and the first metal wiring a 1 at low impedance. They are further electrically connected with the polysilicon wiring PL 2 through the first metal wiring a 3 and the gate contact hole GC at low impedance. This part makes up one memory node (the first metal wirings a 1 and a 3 ) of the SRAM 1 .

The N+ diffused region located in the center of the second P well region and the P+ diffused region located in the lower of the N well region are electrically connected through the diffusion contact hole C and the first metal wiring b 1 at low impedance. They are further electrically connected with the polysilicon wiring PL 1 through the first metal wiring b 3 and the gate contact hole GC at low impedance. This part makes up the other memory node (the first metal wirings b 1 and b 3 ) of the SRAM 1 .

The P+ diffused region located in the center of the N well region is connected with the VDD potential wired through the second metal wiring through the diffusion contact hole C and the like. In FIG. 1 , in order to clarify, the first and the second metal wirings are omitted, which corresponds to the sources of the PMOS transistors P 1 and P 2 in the circuit diagram of FIG. 2 .

The N+ diffused region located in the lower of the first P well region and the N+ diffused region located in the upper of the second P well region each are connected with the GND potential wired with the second metal wiring through the diffusion contact holes C. In FIG. 1 , in order to clarify, the first and the second metal wirings are omitted, which corresponds to the sources of the NMOS transistors N 1 and N 2 in the circuit diagram of FIG. 2 .

The N+ diffused region located in the upper of the first P well region and the N+ diffused region located in the lower of the second P well region each are connected with the bit lines BL 1 and BL 2 wired with the second metal wiring through the diffusion contact holes C.

The polysilicon wirings PL 3 and PL 4 are elongated and wired in a horizontal direction to form the word lines WL 1 and WL 2 .

As is apparent from the above description, according to the first embodiment, the NMOS transistors N 1 and N 3 are formed in the first P well region, and the NMOS transistors N 2 and N 4 are formed in the second P well region, to enable the efficient wiring of the first metal wirings a 3 and b 3 connecting each of the memory nodes mutually, without overlapping the metal wires. Accordingly, the first metal wirings a 3 , b 3 and the first metal wirings a 1 , b 1 can be wired in the same wiring layer. This reduces the number of wiring layers of the semiconductor memory device.

Moreover, the polysilicon wirings PL 1 , PL 2 , PL 3 , and PL 4 are placed in the same direction. This not only facilitates the adjustment of the gate size but also removes a wasted region, resulting in reduction in the region of the semiconductor device.

As is apparent from FIG. 1 , the PMOS transistors P 1 and P 2 are formed such that the source and the drain align in a direction orthogonal to the word lines WL 1 and WL 2 .

Further, the NMOS transistors N 1 and N 3 are formed such that the source and the drain align in a direction orthogonal to the word line WL 1 .

In addition, the NMOS transistors N 2 and N 4 are formed such that the source and the drain align in a direction orthogonal to the word line WL 2 .

This narrows the widths of the P and the N well regions.

Second Embodiment

In the first embodiment, the semiconductor memory device made up of the one-bit SRAM is shown. In the case where the semiconductor memory device is a plural-bits SRAM, the semiconductor memory device should be formed into the layout configuration such as shown in FIG. 3 . FIG. 4 is a circuit diagram showing the semiconductor memory device shown in FIG. 3 .

In the second embodiment, the source of the NMOS transistor N 2 of a memory cell m 1 is connected to the N+ diffused region (corresponding to the N+ diffused region located in the lower of the first P well region in FIG. 1 ) to which the source of the NMOS transistor N 1 of a memory cell m 0 is connected to share the N+ diffused region.

Similarly, the source of the NMOS transistor N 1 of a memory cell m 2 is connected to the N+ diffused region (corresponding to the N+ diffused region located in the upper of the second P well region in FIG. 1 ) to which the source of the NMOS transistor N 2 of the memory cell m 0 is connected to share the N+ diffused region.

When such layout configuration is taken, a plurality of memory cells can be fitted together like jigsaws. This removes a wasted region and reduces the region of the semiconductor device.

The bit lines BL 1 and BL 2 connected with the drains of the NMOS transistors N 3 and N 4 in each of memory cells are wired such that a power line or a ground line is placed between the bit lines as shown in FIG. 3 , without adjoining to each other on the second layer.

This shields the bit lines by the VDD potential or the GND potential, and therefore suppresses interference between the bit lines caused by cross talk and the like.

Third Embodiment

While in the first embodiment, the NMOS transistors N 1 and N 3 are formed in the first P well region, and the NMOS transistors N 2 and N 4 are formed in the second P well region by dividing a P well region, the PMOS transistor P 1 may be formed in the first N well region, and PMOS transistor P 2 may be formed in the second N well region by dividing a N well region as in FIGS. 5 and 6 . In this event, the same effect as the first embodiment can be obtained.

The arrangement of the other parts can be easily inferred from the description in the first embodiment, so more detailed description thereof is omitted. The NMOS transistors N 1 , N 2 , N 3 , and N 4 are formed in a P well region. At that time, the NMOS transistors N 1 , N 2 , N 3 , and N 4 are formed such that the sources and drains thereof align in a direction orthogonal to the word lines WL 1 and WL 2 .

The sources of NMOS transistors N 1 and N 2 are connected with the ground potential of a N+ diffused region formed in P well region.

Fourth Embodiment

While in the third embodiment the semiconductor memory device made up of one-bit SRAM is shown, in the case where the semiconductor memory device is a plural-bits SRAM, the semiconductor memory device should be formed into the layout configuration such as shown in FIG. 7 . FIG. 8 is a circuit diagram showing the semiconductor memory device shown in FIG. 7 .

In the fourth embodiment, the source of PMOS transistor P 2 of the memory cell m 1 is connected to the P+ diffused region to which the source of PMOS transistor P 1 of the memory cell m 0 is connected to share the P+ diffused region.

Similarly, the source of the PMOS transistor P 1 of the memory cell m 2 is connected to the P+ diffused region to which the source of the PMOS transistor P 2 of memory cell m 0 is connected to share the P+ diffused region.

When such a layout configuration is taken, a plurality of memory cells can be fitted together like jigsaws. This removes a wasted region and reduces the region of the semiconductor device.

The bit lines BL 1 and BL 2 connected with the drains of the NMOS transistors N 3 and N 4 in each of memory cells are wired such that a power line or a ground line is placed between the bit lines, without adjoining to each other on the second layer as shown in FIG. 7 .

This shields the bit lines by the VDD potential or the GND potential, and therefore suppresses interference between the bit lines caused by cross talk and the like.