Method for producing defined polycrystalline silicon areas in an amorphous silicon layer

The present invention relates to a method of producing well-defined polycrystalline silicon areas, in particular for producing electrically conducting regions.

Electrically conducting regions may be defined in an amorphous silicon layer by controlled production of polycrystalline silicon regions. Such polycrystalline silicon regions may be characterized by a good electric conductivity, which may optionally be adjusted by introducing suitable dopants. Furthermore, polycrystalline silicon has a high piezoresistivity, so it may be suitable for use of wire strain gauges. Such wire strain gauges may be used in pressure sensors, for example. An electric resistance, which may be determined via a corresponding analyzer circuit, changes due to the acting pressure.

Polycrystalline silicon may be produced by a LPCVD method (low-pressure chemical vapor deposition), where the deposition rate may be determined by the process temperature. The process temperatures may vary in ranges between 400° C. and 900° C., depending on the layer of polycrystalline silicon to be deposited.

If such polycrystalline silicon layers are deposited on heat-sensitive substrates, e.g., stainless steel substrates, to produce high-pressure sensors, the high thermal stress associated with such deposition may constitute a high process risk. To define geometrically the electrically conducting regions, they may be well-defined by photolithographic process steps. This may require that a masking layer be applied to the polysilicon layer and exposed, then the exposed or unexposed regions be removed selectively and next the polysilicon layer may be plasma etched, for example. Such methods may be relatively complicated to control and may allow only a limited structural fidelity.

An exemplary method according to the present invention may reduce a thermal load in production of polycrystalline silicon regions. Furthermore, an exact structural definition may be achieved so that process reliability and yield may be increased. In situ high resolution structuring of the polycrystalline silicon regions in the submicrometer range may be possible because a substrate may be provided with a layer of a doped amorphous silicon, the amorphous silicon may be irradiated using a laser source to produce the electrically conducting regions, a shadow mask being positioned between the substrate and the laser source to provide definition of the electrically conducting regions. Irradiation of the doped amorphous silicon using a laser source, in particular an excimer laser, may permit a controlled breakup of the bond structure of the amorphous silicon through direct electronic energization and production of a polycrystalline lattice structure as a function of the wavelength used and the duration of the laser treatment. Polycrystalline silicon having a high electric conductivity, a low temperature dependence of the resistance, and a marked piezoresistivity may be obtained by previously doping the amorphous silicon. Use of the shadow masks in laser treatment may also eliminate a requirement for photolithographic process steps. This may reduce manufacturing costs on the whole.

FIGS. 1 a through 1 e show manufacturing steps in the production of polycrystalline silicon regions in a first exemplary embodiment.

FIGS. 2 a through 2 f show process steps for production of polycrystalline silicon regions in a second exemplary embodiment.

FIGS. 1 a through 1 e show schematically individual process steps in the production of well-defined polycrystalline silicon regions by an exemplary method according to the present invention. A silicon oxide (SiO 2 ) layer 12 is first applied to a substrate 10 , e.g., a stainless steel substrate. Then as illustrated in FIG. 1 b , a layer 14 of doped amorphous silicon is deposited on this layer 12 . Then as illustrated in FIG. 1 c , a passivation layer 16 , e.g., of silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ) is applied.

In a next step illustrated in FIG. 1 d , the composite of layers 10 , 12 , 14 , 16 is irradiated with a laser source 18 , e.g., an excimer laser, using electromagnetic radiation 20 . A shadow mask 22 having at least one mask opening 24 is arranged between laser source 18 and the composite of layers 10 , 12 , 14 , 16 . In the area of mask opening 24 , electromagnetic radiation 20 strikes the composite of layers 10 , 12 , 14 , 16 . Passivation layer 16 is transparent to electromagnetic radiation 20 . Crystallization occurs in the area of amorphous silicon layer 14 —well-defined geometrically by the mask opening—due to irradiation with electromagnetic radiation 20 , so that a polycrystalline silicon region 26 develops there. According to the contour of mask opening 24 , region 26 of the polycrystalline silicon is defined and is embedded in layer 14 of amorphous silicon. Due to the doping of amorphous silicon 14 , an electrically highly conductive polycrystalline silicon region 26 is formed. Since amorphous silicon 14 has a relatively high resistance and polycrystalline region 26 has a high electric conductivity, the electrically conductive regions are well-defined by region 26 .

Then as illustrated in FIG. 1 e , contact windows 28 are opened in passivation layer 16 , and a metallic coating (not shown here) is subsequently deposited in these windows. This metallic coating provides contacting of electrically conducting region 26 .

Contact windows 28 may likewise be opened by irradiation with a laser light. In this manner, contact windows 28 may be selectively opened by changing the wavelength of the laser light, for example, and/or increasing the power of laser source 18 and providing a suitable shadow mask.

Photolithographic process steps may not be required for production of well-defined electrically conductive regions 26 of polycrystalline silicon. Furthermore, irradiation with laser light may not be critical thermally, so that substrate 10 is not exposed to an excessive thermal load. In this manner, electrically conducting regions 26 may be produced with a high process reliability and a high process rate.

The exemplary method according to the present invention may be used, for example, in the production of high-pressure sensors in which substrate 10 is made of a stainless steel and electrically conducting regions 26 form wire strain gauges in a bridge circuit (e.g., a Wheatstone bridge). This may require only an appropriately adapted configuration of shadow mask 22 , which has an appropriate number of mask openings 4 (e.g., four in this case) for definition of the bridge resistors and corresponding openings to form the feeder lines (printed conductors). In the case of high-pressure sensors having stainless steel substrates or other structural components having non-silicon wafer substrates, the exemplary method according to the present invention may be desirable because it may eliminate the use of conventional photolithography which with these components may be a yield-limiting process that may be difficult to control.

FIGS. 2 a through 2 f illustrate another exemplary method according to the present invention. The same parts as in FIG. 1 are provided here with the same reference numbers and will not be explained again here, so that only the differences will be discussed.

In contrast with the exemplary embodiment illustrated in FIGS. 1 a through 1 e , polycrystalline silicon region 26 is structured before deposition of passivation layer 16 . This may make it possible, as illustrated in FIG. 2 d , to selectively remove the regions of amorphous silicon (former layer 14 ) surrounding polycrystalline silicon regions 26 produced then. Because of the prevailing etching selectivity between amorphous silicon and polycrystalline silicon, which may be particularly pronounced in the case of strong boron doping, this may be implemented by an etching attack, e.g., through the use of plasmas containing hydrogen or halogen, in a simple manner without a photolithography step. Following this, as illustrated in FIG. 2 e , passivation layer 16 is deposited and then ( FIG. 2 f ) contact windows 28 are structured therein. These windows are then metal plated again so that polycrystalline silicon regions 26 may be connected to an electric circuit.

In the first exemplary embodiment, the process steps illustrated in FIGS. 1 a , 1 b and 1 c , and in the second exemplary embodiment, the steps illustrated in FIGS. 2 a and 2 b may be performed immediately in succession in one recipient without any negative effect on the vacuum atmosphere required in the meantime, or at least having to release the vacuum. This may yield on the whole a shorter process running time. Also, a thermal stress on substrate 10 may be greatly reduced in comparison with the conventional LPCVD deposition method for polycrystalline silicon. In addition, due to the prior doping of amorphous silicon in layer 14 and the subsequent well-defined exposure of regions 26 to electromagnetic radiation 20 , very homogeneous polycrystalline silicon regions 26 may be obtained, resulting in a considerable reduction in asymmetry in the entire bridge when used as wire strain gauges in a Wheatstone resistance bridge, so that high-precision piezoresistive pressure sensors may be produced through this exemplary method according to the present invention.