Systems and methods for refreshing non-volatile memory

1. Field of the Invention

The present invention relates to non-volatile, rewritable memory and in particular, to methods and systems for refreshing non-volatile, rewritable memory arrays.

2. Description of the Related Art

In a typical FLASH memory array, the memory cells are arranged in a rectangular array of rows and columns to form intersections at which there are disposed memory cell transistors. The drain of each transistor is connected to a corresponding bit line, the source of each transistor is connected to an array source voltage by an array source line, and the gate of each transistor is connected to a wordline.

Typical FLASH memories allow cells to programmed, read or erased in bulk, sectors or pages. In addition, some FLASH memories can be operated in an EEPROM mode, where from the user perspective, cells can be programmed, read or erased on a byte basis. Cells are conventionally programmed by driving selected bit lines connected to the memory cell transistor drains to a first voltage and driving the gates of the memory cell transistors connected to selected wordlines to a second higher voltage to perform hot electron injection.

The erasure of FLASH memory cell data is performed by driving the gate of a memory cell transistor to a voltage that is substantially less than a voltage placed on the bit line. In doing so, electrons are tunneled off of the floating gate of the memory cell transistor. By way of example, the erase operation can be performed as a bulk erase, which erases the entire FLASH memory array, a sector erase, which erases a FLASH memory array sector, or a page erase, which erases a single sector row. If the FLASH memory can be operated in an EEPROM mode, then the erasure can, from the user perspective, be performed on a byte basis.

However, FLASH memories are subject to a disturb phenomenon during erase and program operations. Because memory cells may share the same bit lines across sectors, voltages placed on these bit lines produce electrical field effects on the sectors sharing the bit lines. Furthermore, memory cells within different sectors may share wordlines, and voltages on these shared wordlines create field effects in the sectors sharing them.

The electric fields generated on the shared bit lines and wordlines may have the effect of inadvertently erasing programmed bits or programming erased bits. For example, raising the voltage on a wordline to program an erased bit may disturb a previously programmed bit on the same wordline by removing some electrons from the floating gate to the control gate of the previously programmed bit. Thus, the sector cells need to be refreshed after each erase or program operation or after a predetermined number of erase or program cycles.

One conventional technique for performing refresh operations is to perform a refresh on an entire sector after each erase/program operation, where the contents of the sector to be refreshed are buffered and then rewritten. However, the buffer used to store the sector contents utilizes a significant amount of area and so the sector size may need to be constrained to reduce the buffer size. Another conventional technique for determining when to perform a refresh operation is to count the number of erase or program cycles using a counter, and performing a refresh after a predetermined number of cycles. However, such counters are often of insufficient reliability. Hence these conventional refresh techniques fail to provide a refresh process that is both efficient and reliable.

The present invention is directed to methods and systems for refreshing non-volatile memories, such as FLASH memories that can be operated in an EEPROM mode. In particular, one embodiment of the present invention embeds a refresh process in a write operation. After each program/erase cycle, a refresh operation is performed beginning at the byte cells associated with the selected bit line and proceeding sequentially. In one embodiment, a cell current is measured, and if the cell current meets a first criteria, the cell is refreshed.

In particular, a predetermined amount of time is allocated for performing a refresh process, including both the actual refresh and a verify process. Using an embodiment of the present invention, if the cells associated with a wordline can sustain more than N cycles without needing to be refreshed, then 1/N sectors can be sequentially refreshed after each erase or program operation. This is in contrast to some conventional techniques that refresh an entire sector after each erase or program operation. Advantageously, the present invention reduces the size needed for a refresh buffer and enables enlargement of the sector size by a factor N, without use of a refresh cycle counter.

In particular, a write or rewrite operation includes 3 embedded operations: an erase operation, a program operation, and a refresh operation. During the refresh operation, a FLASH cell floating gate is charged using Channel Hot Electron injection (CHE) by providing a high bias on the gate and an elevate bias on the drain. In one embodiment, a cell is refreshed when the cell current falls within a predetermined range. Thus, rather then refreshing every cell within a sector when performing a refresh operation, the refresh operation is performed on those cells whose cell current falls within a predetermined range.

FIG. 1 illustrates an example block diagram of a FLASH memory circuit in accordance with one embodiment of the present invention. FIG. 2 illustrates a schematic of an example portion of a FLASH memory circuit.

FIG. 3 illustrates a flow diagram of one example method of refreshing a FLASH memory circuit.

FIG. 4 illustrates a flow diagram of the example method of refreshing a FLASH memory circuit illustrated in FIG. 3 in greater detail.

FIG. 5 illustrates an example embodiment of a sequential bit line refresh process.

FIG. 6 illustrates an example I-V curve graph.

Throughout the drawings, like reference numbers are used to reference items that are identical or functionally similar.

For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Embodiments of the present invention are related to methods and systems for refreshing re-writable non-volatile solid-state memory memories. In particular, a refresh operation is embedded in a write or rewrite operation. As is described in greater detail below, in one embodiment after a byte is rewritten, a refresh operation is performed within a predetermined amount of time starting from the bit line selected during the rewrite operation.

Advantageously, rather then refreshing every cell within a sector when a refresh operation is performed, the refresh operation is performed when a given cell's cell current falls within a predetermined range. For example, perhaps only 1% of the cells will have cell currents that fall within the predetermined range. Thus, the refresh process is both quicker and utilizes less buffer space than many conventional approaches. Optionally, the refresh process is embedded in a write or a rewrite operation that further includes erase and program operations. After each program/erase cycle, a refresh operation is performed beginning at the byte cells associated with the selected bit line and proceeding sequentially.

It will be understood that the circuits, voltage, currents, and the like described below are for illustrative purposes only. Thus, the invention may be embodied or carried out using other circuits, voltages and/or currents.

FIG. 1 illustrates an example block diagram of a portion of a non-volatile memory circuit 100 in accordance with one embodiment of the present invention. Advantageously, the memory circuit is configured to act in both EEPROM and FLASH memory modes. In the EEPROM mode, data can be written a byte at a time, while in FLASH mode, data can be written a sector or page at a time. The memory circuit 100 includes a plurality of sectors 102 , 104 , 106 , 108 , 110 , 112 of memory cells coupled to a column decoder 134 and a wordline decoder 112 . Sectors 102 , 104 , 106 share common bit lines 120 from the column decoder 134 and sectors 108 , 110 , 112 share common bit lines 122 from the column decoder 134 . Sectors 102 and 108 share common wordlines 124 from wordline decoder 130 , sectors 104 and 110 share common wordlines 126 from the wordline decoder 130 , and sectors 106 and 112 share common wordlines 128 from the wordline decoder 130 . More generally, each wordline represents one of M rows, wherein each of the M rows has N words. The number of bit lines is the same as the number of N words in a row multiplied by the number of bits in each word.

An Erase/Program/Read circuit 114 is coupled to the column decoder 134 and the wordline decoder 130 . A refresh circuit 118 is coupled to the Erase/Program/Read circuit 114 , the column decoder 134 , and the wordline decoder 130 . As described in greater detail below the refresh circuit 118 is used to appropriately refresh cells to ensure that disturb conditions do alter data. A disturb condition can arise because memory cells share the same bit lines across sectors, so that voltages placed on these bit lines produce electrical field effects on the sectors sharing the bit lines. A disturb condition can also arise because memory cells within different sectors may share wordlines, and voltages on these shared wordlines create field effects in the sectors sharing them. Thus, erasing one sector can inadvertently cause the values of bits in other sectors to change, and so a refresh operations needs to be performed so that the values do not inadvertently change.

FIG. 2 illustrates a schematic of an example portion 200 of a FLASH memory circuit sector, such as sector 102 illustrated in FIG. 1 . The example sector includes 32 cells per bit line and has 32 wordlines (WL), with 256 bytes connected to the same wordline driver. Each memory cell is coupled to one wordline and one bit line. For each of the cells disposed at the intersection of a wordline and a bit line, the drain of the cell is connected to the bit line, the source of the cell is connected to an array source voltage by an array source line, and the gate of the cell is connected to the wordline. For example, memory cell 202 has a control gate coupled to wordline 204 , a drain coupled to bit line 204 and a source connected to the array source line (S). In the example embodiment, the sources of the memory cells within a particular sector are commonly coupled to the array source line (S). A sense amplifier 132 , as illustrated in FIG. 1, reads selected bits.

As described in greater detail below, a rewrite process includes 3 operations: an erase operation, a program operation, and a refresh operation. During the refresh operation, a memory cell floating gate is charged using Channel Hot Electron injection (CHE) by providing a high bias on the gate and an elevated bias on the drain.

FIG. 3 illustrates an example rewrite process 300 used when the non-volatile solid-state memory 100 is being operated in a byte erasable mode. Beginning at state 302 , an addressed byte in a first sector is erased. Proceeding to state 304 , the addressed byte is then programmed with the desired data. Proceeding to state 306 , the refresh operation is performed, starting from the selected bit line, then proceeding sequentially through the next bit lines until the entire sector undergoes the refresh process. Optionally, a fixed period of time, such as 1 ms or 2 ms, can be allocated to perform the refresh process of state 306 . The process performed at state 306 is illustrated in greater detail in FIG. 4, as discussed below.

Referring to FIG. 4, the example refresh process 306 is illustrated in greater detail. As discussed below, the automatic refresh operation determines if the memory cell or cells has a property, such as current, that has reached a threshold value or is within in a desired range, and if so, performs a refresh of the memory cell or cells. Thus, rather then refreshing every cell within a sector, the refresh operation is performed when the cell current falls within a predetermined range. Starting at state 402 , the process 306 proceeds to state 404 , where the cell control gate is set to a program verify voltage level (V g ) and the memory cell is read. By way of example, V g may be set to 7 Volts.

At state 406 the cell current Icell is measured to determine if Icell is greater than a predetermined threshold value I 1 , which may be, by way of example 20 μA. If the value of Icell is less than or equal to I 1 , then a refresh will not be performed and the process 306 proceeds to state 414 . If the value of Icell is greater than I 1 , then the process 306 proceeds to state 408 . At state 408 the cell current Icell is measured to determine if Icell is less than a predetermined threshold value 12 , which may be, by way of example 40 μA. If the value of Icell is greater than or equal to I 2 , then a refresh will not be performed and the process 306 proceeds to state 412 . If the value of Icell is less than I 2 , then the process 306 proceeds to state 410 . At state 410 the refresh operation is performed.

At state 412 a determination is made as to whether the last sector byte has been evaluated to determine if it is to be refreshed. If it is the last byte, the process 306 ends at state 412 . Otherwise, the process 306 proceeds to state 413 , where the cell evaluation process proceeds to the next byte associated with the sequentially next bit line, then loops back to state 404 , and the process is repeated. Because not all cells in a given sector are refreshed in the same refresh cycle, the time allocated for the refresh operation is greatly reduced. For example, for some array embodiments, only 1% of the cells need to be refreshed at a given time.

FIG. 5 illustrates at a high level the refresh sequence. Beginning with the selected bit line BLO, the refresh operation is performed on cells meeting the current criteria and associated with the bit line selected during the program/erase process. Then, cells associated with the subsequent sector bit lines that meet the current criteria are refreshed.

By way of example, using an embodiment of the present invention, if the memory array cells have a 100 cycle endurance at −6.5V V g before needing to be refreshed, and if the array has 32 cells per bit line as illustrated in FIG. 2, the bytes which are to be refreshed include cells associated with the selected and subsequent bit lines. If the setup overhead per byte is 1.5 μs, the refresh time per byte is 1.5 μs, and 2 wordlines are connected to one wordline driver, with 128 bytes sharing the same wordline, the refresh time that needs to be allocated is less then 1 ms.

Table 1 above includes example EEPROM operation conditions and the corresponding cell effects. A significant area of interest is the cell state in the range from high Vt to low Vt. With the program voltage set to 5V and the erase terminal floated, VD (the drain voltage) at program disturbs the cell state from high Vt to low Vt. With the program voltage set to 11V and the erase terminal set to −7V, VG (the gate voltage) at erase disturbs the cell state from high Vt to low Vt. With the program voltage set to 0V and the erase terminal set to 6V, VS (the source voltage) at erase disturbs the cell state from high Vt to low Vt. With the program voltage set to 0V and the erase terminal set to 0V, there is no effect.

FIG. 6 illustrates an example Flash cell I-V curve graph for the cell current definition during the refresh determination process illustrated in FIG. 4B, and in particular, at states 406 and 408 . The example read voltage is 7V, the lower bound for the cell current Icell is I 1 at 20 μA, and the upper bound for the cell current Icell is I 2 at 40 μA. If I 1 <Icell<I 2 , the cell will be refreshed. If Icell≦I 1 , then no refresh will be performed. Similarly, if Icell≧I 2 , then no refresh will be performed.

Table 2 below describes example memory array operation modes.

When programming a whole sector in FLASH mode, no refresh operation is required. In EEPROM byte mode, when one byte is to be rewritten, first the corresponding byte is erased. Then the byte is programmed. The refresh operation as illustrated in FIG. 4 is then performed.

When operating in FLASH mode, a sector erase is optionally performed by erasing the entire sector. When operating in FLASH mode, a sector erase and sector program operation is performed by first performing an erase sector operation and then performing a sector program operation. No refresh operation need be performed.

Thus as discussed above, embodiments of the present invention provide reliable and efficient methods for refreshing non-volatile memories. In particular, a refresh process is embedded in a write operation, and cells are evaluated to determine if the cells are is refreshed.

Although this invention has been described in terms of certain preferred embodiments, other embodiments that are apparent to those of ordinary skill in the art are also within the scope of this invention.