NOR-structured semiconductor memory device

A. Field of the Invention

The present invention relates to a semiconductor memory device and, more particularly, to a NOR-structured semiconductor memory device with a novel configuration of bit line connection.

B. Description of the Related Art

FIG. 1 is a schematic diagram showing a conventional NOR-structured semiconductor memory device 1 . For the sake of descriptive simplicity, the conventional NOR-structured memory device 1 shown in FIG. 1 includes a 2×8 memory cell array whose memory cells are electrically connected to corresponding word lines and bit lines. More specifically, the memory cells arranged in a row are electrically connected in parallel to a word line while the memory cells arranged in a column are electrically connected in parallel to two adjacent bit lines. For example, memory cells M 10 to M 17 are arranged in such a way that the gate electrodes of them are electrically connected in parallel to a word line WL 1 . Memory cells M 10 and M 00 are arranged in such a way that the channel electrodes (i.e., source and drain electrodes) of them are electrically connected in parallel to two adjacent bit lines BL 0 and BL 1 , respectively.

Referring to FIG. 1, bit lines BL 0 and BL 2 are coupled to a main bit line MBL 0 through bit line transistors BLT 0 and BLT 1 , respectively. Bit lines BL 1 and BL 3 are coupled to a main bit line MBL 2 through bit line transistors BLT 4 and BLT 5 , respectively. The bit line transistors BLT 0 , BLT 1 , BTL 4 , and BLT 5 may be N-type MOS (Metal-Oxide-Semiconductor) transistors and become conductive or non-conductive in response to selection signals input from selection lines SEL 0 , SEL 1 , SEL 2 , and SEL 3 , respectively. Similarly, bit lines BL 4 and BL 6 are coupled to a main bit line MBL 1 through bit line transistors BLT 2 and BLT 3 , respectively, while bit lines BL 5 and BL 7 are coupled to a main bit line MBL 3 through bit line transistors BLT 6 and BLT 7 , respectively. The bit line transistors BLT 2 , BLT 3 , BTL 6 , and BLT 7 may be N-type MOS transistors and become conductive or non-conductive in response to selection signals input from selection lines SEL 0 , SEL 1 , SEL 2 , and SEL 3 , respectively.

The memory cells M 00 to M 07 and M 10 to M 17 may be programmable memory devices such as EPROM (Erasable Programmable Read Only Memory) or Flash EEPROM. In this case, the programming operation of a selected memory cell in the conventional NOR-structured memory device is described as follows. To program the memory cell M 00 for example, the word line WL 0 is activated and the selection lines SEL 0 and SEL 2 are activated to turn on the bit line transistors BLT 0 and BLT 4 . In addition, the selection lines SEL 1 and SEL 3 are deactivated to turn off the bit line transistors BLT 1 and BLT 5 . At the same time, the main bit line MBL 2 is supplied with a high programming voltage and the main bit lines MBL 0 , MBL 1 , and MBL 3 are all grounded. Therefore, the memory cell M 00 is programmed through a current path L 1 consisting of the main bit line MBL 2 , the bit line transistor BLT 4 , the bit line BL 1 , the bit line BL 0 , and the bit line transistor BLT 0 , and the main bit line MBL 0 .

During the programming operation of the memory cell M 00 , however, the memory cells M 01 , M 02 , M 03 , and M 04 are simultaneously activated by the word line WL 1 and subject to programming disturbance by the high programming voltage from the main bit line MBL 2 since two other current paths L 2 and L 3 are formed as shown in FIG. 1 . Therefore, it is desirable to provide a NOR-structured semiconductor memory device capable of preventing the programming disturbance during the programming operation.

There is also a problem in the conventional NOR-structured semiconductor memory device during the data reading operation. To read the data stored in the memory cell M 00 for example, a sense current is supplied to the main bit line MBL 2 . If the memory cell M 00 is turned off at the activation of the word line WL 0 , the potential of the main bit line MBL 2 increases because no current path L 1 is formed. Subsequently, the potential of the main bit line MBL 2 is sensed and the data reading operation of the memory cell M 00 is finished. During the data reading operation of the memory cell M 00 , however, the above-mentioned leakage current paths L 2 and L 3 as a result of the simultaneous activation of the memory cells M 01 , M 02 , M 03 , and M 04 by the word line WL 0 cause that it takes a longer time to raise the potential of the main bit line MBL 2 . In other words, it is difficult for a conventional NOR-structured semiconductor device shown in FIG. 1 to achieve high-speed data reading operations. In some cases, the leakage current paths L 2 and L 3 even make the sensed potential of the main bit line MBL 2 become such a low value that the memory cell M 00 is falsely determined as a turned-on cell. Therefore, it is desirable to provide a NOR-structured semiconductor memory device with high-speed data reading operations and correct data determinations.

In view of the above-mentioned problems of the conventional NOR-structured semiconductor memory device, it is an object of the present invention to provide a novel NOR-structured semiconductor memory device capable of preventing the programming disturbance during programming operations.

It is another object of the present invention to provide a novel NOR-structured semiconductor memory device with high-speed data reading operations.

It is still another object of the present invention to provide a novel NOR-structured semiconductor memory device in which the data stored in memory cells are correctly determined.

According to the present invention, a NOR-structured semiconductor memory device is provided with a semiconductor memory cell array having a plurality of semiconductor memory cells. The plurality of semiconductor memory cells may consist of programmable cells, such as EPROM or Flash EEPROM. A plurality of bit lines are electrically connected to the semiconductor memory cell array and divided into at least four bit line groups. At least two bit lines of each bit line group of the at least four bit line groups are coupled to a main bit line through at least two bit line transistors, respectively. The main bit line serves as a common main bit line for the coupled at least two bit lines. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively.

During programming operations, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device according to the present invention successfully prevents the programming disturbance because no leakage current path is formed.

During data reading operations, two adjacent bit lines of the four adjacent bit lines are supplied with a sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device according to the present invention correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.

Above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following detailed descriptions and accompanying drawings, wherein:

FIG. 1 is a schematic diagram showing a conventional NOR-structured semiconductor memory device;

FIG. 2 is a schematic diagram showing a NOR-structured semiconductor memory device of an embodiment according to the present invention; and

FIG. 3 is a schematic diagram showing a NOR-structured semiconductor memory device of another embodiment according to the present invention.

The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram showing a NOR-structured semiconductor memory device 2 of an embodiment according to the present invention. For the sake of descriptive simplicity, the NOR-structured memory device 2 shown in FIG. 2 includes a 2×8 memory cell array whose memory cells are programmable cells, such as EPROM or Flash EEPROM, and electrically connected to corresponding word lines and bit lines. It should be noted that the present invention is applicable to any NOR-structured semiconductor memory device regardless of the array size and programmability of the memory cell. More specifically, the present invention is applicable to a NOR-structured semiconductor memory device having an mxn programmable memory cell array wherein m and n are both natural numbers.

The memory cells arranged in a row are electrically connected in parallel to a word line while the memory cells arranged in a column are electrically connected in parallel to two adjacent bit lines. For example, memory cells M 10 to M 17 are arranged in such a way that the gate electrodes of them are electrically connected to a word line WL 1 . Memory cells M 10 and M 00 are arranged in such a way that the channel electrodes (i.e., source and drain electrodes) of them are electrically connected in parallel to two adjacent bit lines BL 0 and BL 1 , respectively.

Referring to FIG. 2, bit lines BL 0 and BL 4 are coupled to a main bit line MBL 0 through bit line transistors BLT 0 and BLT 1 , respectively. Bit lines BL 1 and BL 5 are coupled to a main bit line MBL 1 through bit line transistors BLT 2 and BLT 3 , respectively. Similarly, bit lines BL 2 and BL 6 are coupled to a main bit line MBL 2 through bit line transistors BLT 4 and BLT 5 , respectively. Bit lines BL 3 and BL 7 are coupled to a main bit line MBL 3 through bit line transistors BLT 6 and BLT 7 , respectively. The bit line transistors BLT 0 and BLT 2 are electrically connected at gate electrodes to a selection line SELO while the bit line transistors BLT 1 and BLT 3 are electrically connected at gate electrodes to a selection line SEL 1 . Similarly, the bit line transistors BLT 4 and BLT 6 are electrically connected at gate electrodes to a selection line SEL 2 while the bit line transistors BLT 5 and BLT 7 are electrically connected at gate electrodes to a selection line SEL 3 . Consequently, two bit line transistors coupled together to a main bit line are controlled by two different selection lines.

The NOR-structured semiconductor memory device according to the present invention is characterized in that at least four adjacent bit lines thereof are coupled to four different main bit lines through four different bit line transistors, respectively. Such a configuration of bit line connection can prevent the programming disturbance during programming operations and achieve high-speed data reading operations as well as correct data determinations.

For example, the four adjacent bit lines BL 0 , BL 1 , BL 2 , and BL 3 are coupled to four different main bit lines MBL 0 , MBL 1 , MBL 2 , and MBL 3 through four different bit line transistors BLT 0 , BLT 2 , BLT 4 , and BLT 6 , respectively, as shown in FIG. 2 . Now assume that the memory cell M 01 is to be programmed. The word line WL 0 is activated and the selection lines SEL 0 and SEL 2 are activated to turn on the bit line transistors BLT 2 and BLT 4 . Moreover, the selection lines SEL 1 and SEL 3 are deactivated to turn off the bit line transistors BLT 3 and BLT 5 . At the same time, the main bit line MBL 2 is supplied with a programming voltage and the main bit line MBLI is grounded. Therefore, the memory cell M 01 is programmed through a current path L 4 consisting of the main bit line MBL 2 , the bit line transistor BLT 4 , the bit line BL 2 , the bit line BL 1 , and the bit line transistor BLT 2 , and the main bit line MBL 1 .

In order to prevent the memory cells adjacent to the memory cell M 01 (i.e., M 00 and M 02 ) from the programming disturbance, the programming voltage supplied to the main bit line MBL 2 is also supplied to the main bit line MBL 3 and the main bit line MBL 0 is, like the main bit line MBL 1 , grounded. Because the bit line transistors BLT 0 and BLT 6 are, like the bit line transistors BLT 2 and BLT 4 , turned on by the activation of the selection lines SEL 0 and SEL 2 , respectively, nodes A and B are both at a substantially equal potential and nodes C and D are both at another substantially equal potential. As a result, there is no leakage current path formed through the memory cells M 00 and M 02 . Therefore, The NOR-structured semiconductor memory device according to the present invention successfully prevents the programming disturbance during the programming operation.

Now assume that the memory cell M 10 is subject to a data reading operation. The word line WL 0 is activated and the selection lines SEL 0 and SEL 2 are activated to turn on the bit line transistors BLT 2 and BLT 4 . Moreover, the selection lines SEL 1 and SEL 3 are deactivated to turn off the bit line transistors BLT 3 and BLT 5 . At the same time, the main bit line MBL 2 is supplied with a sense current and the main bit line MBL 1 is grounded. According to the present invention, the sense current supplied to the main bit line MBL 2 is also supplied to the main bit line MBL 3 and the main bit line MBL 0 is, like the main bit line MBL 1 , grounded. As a result, there is no leakage current path formed through the memory cells M 00 and M 02 since there is no potential difference between nodes A and B as well as between nodes C and D. Therefore, the potential of the main bit line MBL 2 can increase at a high speed if the memory cell M 00 is turned off at the activation of the word line WL 0 . The NOR-structured semiconductor memory device according to the present invention correctly determines the data stored in the memory cell M 00 at a high speed.

FIG. 3 is a schematic diagram showing a NOR-structured semiconductor memory device 3 of another embodiment according to the present invention. Like the embodiment shown in FIG. 2, at least four adjacent bit lines of the NOR-structured semiconductor memory device shown in FIG. 3 are coupled to four different main bit lines through four different bit line transistors, respectively. The difference between the embodiments shown in FIGS. 2 and 3 is described as follows.

Referring back to FIG. 2, one of two bit lines coupled to a common main bit line is separated from another by four columns of memory cells. In other words, there are three other bit lines arranged between two bit lines coupled to a common main bit line. For example, three bit lines BL 1 to BL 3 are arranged between two bit lines BL 0 and BL 4 coupled to a common main bit line MBL 0 . Referring to FIG. 3, however, one of two bit lines coupled to a common main bit line is separated from another by eight columns of memory cells. In other words, there are seven other bit lines arranged between two bit lines coupled to a common main bit line. For example, seven bit lines BL 1 to BL 7 are arranged between two bit lines BL 0 and BL 8 coupled to a common main bit line MBL 0 . It should be noted that the present invention is applicable to any NOR-structured semiconductor memory device in which one of two bit lines coupled to a common main bit line is separated from another by at least four columns of memory cells or, in other words, there are at least three other bit lines arranged between two bit lines coupled to a common main bit line.

While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.