Inventor

Feng Lin

Inventor

Boise, ID, US

Overview

2002–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 111 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores31%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses24%

G06FElectric digital data processing16%

H03KPulse technique16%

H03HImpedance networks, e.g. resonant circuits3%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

H01LSemiconductor devices2%

H04LTransmission of digital information, e.g. telegraphic communication2%

G01RMeasuring electric variables1%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%

PatentTitleYear

10,530,617Programmable channel equalization for multi-level signaling2020 10,447,512Channel equalization for multi-level signaling2019 10,446,528Apparatuses and methods for scalable memory2019 10,411,704Output impedance calibration for signaling2019 10,325,884Apparatuses and methods for scalable memory2019 10,277,435Method to vertically align multi-level cells2019 10,153,251Apparatuses and methods for scalable memory2018 10,128,842Output impedance calibration for signaling2018 9,564,878'Apparatuses including scalable drivers and methods'2017 RE046005'Method and apparatus for enabling a timing synchronization circuit'2016 9,287,859'Flexible input/output transceiver'2016 9,203,386'Analog delay lines and adaptive biasing'2015 9,153,312'Methods and apparatuses including transmitter circuits'2015 8,836,395'Apparatuses including scalable drivers and methods'2014 8,773,187'Analog delay lines and adaptive biasing'2014 8,749,271'Methods for synchronizing high-speed signals in a digital phase detector'2014 8,587,340'Apparatuses including scalable drivers and methods'2013 8,576,646'Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay'2013 8,570,084'Circuits and methods for clock signal duty-cycle correction'2013 8,536,922'Clock distribution network'2013 8,508,285'Analog delay lines and adaptive biasing'2013 8,392,744'Clock distribution apparatus, systems, and methods'2013 8,330,508'Phase-generation circuitry with duty-cycle correction and method for generating a multiphase signal'2012 8,305,120'Delay locked loop circuit and method'2012 8,289,059'Circuits and methods for clock signal duty-cycle correction'2012 8,289,062'Analog delay lines and adaptive biasing'2012 8,278,993'Clock distribution network'2012 8,183,901'Delay locked loop circuit and method'2012 8,081,020'Delay-lock loop and method adapting itself to operate over a wide frequency range'2011 8,072,838'Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay'2011 8,032,778'Clock distribution apparatus, systems, and methods'2011 8,026,750'Delay locked loop circuit and method'2011 7,999,589'Circuits and methods for clock signal duty-cycle correction'2011 8,001,410'Efficient clocking scheme for ultra high-speed systems'2011 7,961,019'Delay-lock loop and method adapting itself to operate over a wide frequency range'2011 7,948,279'Clock divider'2011 7,888,991'Clock distribution network'2011 7,876,640'Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay'2011 7,812,593'Method for improving stability and lock time for synchronous circuits'2010 7,755,404'Delay locked loop circuit and method'2010 7,725,095'RF circuit with stacked printed circuit boards'2010 7,724,049'Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal'2010 7,688,653'Method and system for improved efficiency of synchronous mirror delays and delay locked loops'2010 7,660,187'Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM'2010 7,639,090'Phase detector for reducing noise'2009 7,619,458'Delay-lock loop and method adapting itself to operate over a wide frequency range'2009 7,605,620'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'2009 7,538,590'Methods and apparatus for dividing a clock signal'2009 7,528,638'Clock signal distribution with reduced parasitic loading effects'2009 7,463,099'Phase detector for reducing noise'2008 7,454,646'Efficient clocking scheme for ultra high-speed systems'2008 7,449,939'Bias generator with feedback control'2008 7,446,580'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'2008 7,443,761'Loop filtering for fast PLL locking'2008 7,443,743'Method and system for improved efficiency of synchronous mirror delays and delay locked loops'2008 7,436,202'Method and apparatus for calibrating driver impedance'2008 7,428,284'Phase detector and method providing rapid locking of delay-lock loops'2008 7,423,919'Method and system for improved efficiency of synchronous mirror delays and delay locked loops'2008 7,420,361'Method for improving stability and lock time for synchronous circuits'2008 7,336,084'Delay lock circuit having self-calibrating loop'2008 7,292,489'Circuits and methods of temperature compensation for refresh oscillator'2007 7,282,972'Bias generator with feedback control'2007 7,276,946'Measure-controlled delay circuits with reduced phase error'2007 7,274,239'Method and apparatus to set a tuning range for an analog delay'2007 7,269,094'Memory system and method for strobing data, command and address signals'2007 7,268,531'Apparatus for improving stability and lock time for synchronous circuits'2007 7,251,194'Memory system and method for strobing data, command and address signals'2007 7,245,553'Memory system and method for strobing data, command and address signals'2007 7,233,180'Circuits and methods of temperature compensation for refresh oscillator'2007 7,230,495'Phase-locked loop circuits with reduced lock time'2007 7,208,986'Measure-controlled delay circuits with reduced phase error'2007 7,206,956'Duty cycle distortion compensation for the data output of a memory device'2007 7,187,617'Memory system and method for strobing data, command and address signals'2007 7,161,399'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'2007 7,158,443'Delay-lock loop and method adapting itself to operate over a wide frequency range'2007 7,145,374'Methods and apparatus for delay circuit'2006 7,138,845'Method and apparatus to set a tuning range for an analog delay'2006 7,132,898'Phase detector for reducing noise'2006 7,129,794'Phase detector for reducing noise'2006 7,129,738'Method and apparatus for calibrating driver impedance'2006 7,126,874'Memory system and method for strobing data, command and address signals'2006 7,123,525'Phase detector for all-digital phase locked and delay locked loops'2006 7,109,807'Phase detector for reducing noise'2006 7,102,361'Delay lock circuit having self-calibrating loop'2006 7,103,791'Interleaved delay line for phase locked and delay locked loops'2006 7,098,714'Centralizing the lock point of a synchronous circuit'2006 7,028,208'Duty cycle distortion compensation for the data output of a memory device'2006 7,020,794'Interleaved delay line for phase locked and delay locked loops'2006 7,009,407'Delay lock circuit having self-calibrating loop'2006 6,992,534'Circuits and methods of temperature compensation for refresh oscillator'2006 6,987,701'Phase detector for all-digital phase locked and delay locked loops'2006 6,950,487'Phase splitter using digital delay locked loops'2005 6,940,328'Methods and apparatus for duty cycle control'2005 6,930,955'Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM'2005 6,930,525'Methods and apparatus for delay circuit'2005 6,912,666'Interleaved delay line for phase locked and delay locked loops'2005 6,895,522'Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock'2005 6,891,415'Method and apparatus for enabling a timing synchronization circuit'2005 6,868,504'Interleaved delay line for phase locked and delay locked loops'2005 6,845,459'System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines'2005 6,845,458'System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines'2005 6,839,301'Method and apparatus for improving stability and lock time for synchronous circuits'2005 6,812,753'System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal'2004 6,798,259'System and method to improve the efficiency of synchronous mirror delays and delay locked loops'2004 6,779,126'Phase detector for all-digital phase locked and delay locked loops'2004 6,774,690'Digital dual-loop DLL design using coarse and fine loops'2004 6,762,974'Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM'2004 6,759,882'System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal'2004 6,618,283'System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal'2003 6,611,475'System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal'2003 6,445,231'Digital dual-loop DLL design using coarse and fine loops'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2020Patents assigned to MICRON TECHNOLOGY INC (109)· patent assignee history

2002–2020Based in Boise, ID, US· patent location history

2006Based in Bosie, ID, US· patent location history

2010Patents assigned to THOMSON LICENSING (1)· patent assignee history

2010Based in Singapore, SG· patent location history

2011–2016Patents assigned to LIN FENG (16)· patent assignee history

2012Patents assigned to ROYER ROMAN ANDREAS (1)· patent assignee history

2016Patents assigned to MIKHALEV VLADIMIR (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	109	2002–2020
LIN FENGself	16	2011–2016
MIKHALEV VLADIMIR	1	2016
ROYER ROMAN ANDREAS	1	2012
THOMSON LICENSING	1	2010

Locations

Location	Patents	Span
Boise, ID, US	109	2002–2020
Singapore, SG	1	2010
Bosie, ID, US	1	2006