System and method to improve the efficiency of synchronous mirror delays and delay locked loops

A method of improving efficiency of a delay-locked loop (DLL), comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB);detecting by way of only a single phase detector four or more timing conditions based upon phases of CIN and CKFB; andselectively inputting a clock signal (CLK) or inverted clock signal (CLK⬲) from a delay line into a clock tree driver (CTD) based on which of the timing conditions is met to reduce a number of effective delay stages in the DLL.

A method of improving efficiency of a delay-locked loop, comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB);interposing a phase detector and selection system between an external clock signal and a clock tree driver (CTD);wherein the selection system is interposed between the clock tree driver (CTD) and a delay linedetermining which of a number of four or more timing conditions is met based upon phases of the signals; andselectively directing the signals based upon the phase of the signals.

A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB), each signal having timing characteristics;differentiating, with only a single phase detector, four or more phases based upon the timing characteristics of CIN and CKFB; andselecting, based on the phases, one of a clock signal (CLK) or inverted clock signal (CLK⬲) from a delay line to be input into a clock tree driver (CTD), to reduce a number of effective delay stages in the DLL.

A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics;determining four or more phases based upon the timing characteristics of CIN and CKFB; andfor at least one phase, directing a clock signal (CLK) from a dealy line into a clock tree driver (CTD) based on the plurality of phases to reduce a number of delay stages.

A memory device, comprising:na delay-locked loop (DLL), comprising:a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector to output a pair of branches each comprising a logical level, wherein the logical levels of the branches define four or more conditions of CIN and CKFB signals based on the timing characteristics, and wherein a clock signal (CLK) or inverted clock signal (CLK⬲) is output from a delay line into a clock tree driver (CTD) based on the plurality of conditions to reduce a number of effective delay stages in the DLL.

A delay-locked loop system, comprising:na delay-locked loop (DLL), comprising:a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector to output a pair of branches each having a logical level; anda delay line, the delay line to receive the CIN and to output a clock signal (CLK) and inverted clock signal (CLK⬲), the CLK and CLK⬲ based on a plurality of conditions, wherein the logical levels of the branches define four or more conditions based on the timing characteristics of CIN and CKFB, and at least one of the conditions reduces a number of effective delay stages in the DLL;wherein the timing characteristics define a period of CIN as tck and a period from a rising edge in CIN to a rising edge in CKFB as te, and the plurality of conditions include:a first condition when te>tck/2;a second condition when te<tck/2;a third condition when te=tck; anda fourth condition when te=tck/2.

A circuit for use with an external clock signal, comprising:nan input buffer comprising an input connected to an external clock signal and an output connected to a clock input signal (CIN), the CIN for comparison with a clock feedback signal (CKFB), each signal comprising timing characteristics;a phase detector disposed between the input buffer and a clock tree driver (CTD), the phase detector comprising a first input for receiving the CIN, and a second input for receiving the CKFB, and generating one of four or more output signal combinations, each combination corresponding to a respective phase of the signals based on the timing characteristics;wherein the circuit includes a delay line, a selection multiplexor connected to the delay line, the CTD to receive an output of the selection multiplexor, and a feedback loop to connect CKFB to the phase detector, the selection multiplexor to selectively input a clock signal (CLK) or inverted clock signal (CLK⬲) from the delay line as an input to the CTD based on the phase of the signals, and for at least one of the phases, a number of effective delay stages of the circuit is reduced.

A delay-locked loop system, comprising:na delay-locked loop (DLL), comprising:a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, and the phase detector to output a pair of branches each comprising a logical level, the logical levels of the branches define four or more conditions based on the timing characteristics, and at least one of the conditions reduces a number of effective delay stages of the DLL; anda delay line, the delay line to receive the CIN and to output a clock signal (CLK) and inverted clock signal (CLK⬲)based on the plurality of conditions.

A phase detection and selection circuit, comprising:na phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, and to generate four or more output signal combinations, each combination based upon the timing characteristics; andlogic associated with the phase detector to select one of the output signal combinations corresponding to the timing characteristics of the signals;to selectively feed at least one of a clock signal (CLK) and an inverted clock signal (CLK⬲) provided at least indirectly by a delay line into a portion of the circuit based upon which of the plurality of output signal combinations is generated, and a number of effective delay stages is reduced.

A system, comprising:na processor;a memory controller;a plurality of memory devices;a first bus interconnecting the processor and memory controller;a second bus interconnecting the memory controller and memory devices;each of the memory devices comprising:a delay-locked loop (DLL), comprising:a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing conditions, and generating a plurality of output signal combinations, each combination corresponding to four or more phases of the signals based upon the timing conditions; andlogic associated with the phase detector to select one of the output signal combinations corresponding to the timing conditions of the signals;wherein the timing conditions include a period of CIN (tck) and a period from a rising edge in CIN to a rising edge in CKFB (te), and selectively inputting CLK into a clock tree driver (CTD) when te<tck/2 reduces a number of effective delay stages.

A synchronous dynamic random access memory (SDRAM), comprising:na delay-locked loop (DLL), comprising:a phase detection system, comprising:a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector comprising a pair of registers, the registers comprising a pair of inputs and a pair of outputs, each of the outputs having a logical level, to define a plurality of output signal combinations, each of the output signal combinations representative of a phase based upon the timing characteristics of the CIN and CKFB, and at least one of the phases reduces a lock period of the CIN to achieve locking with an external clock signal with respect to another phase; andan input selection multiplexor to select whether to input a clock signal (CLK) or an inverted clock signal (CLK⬲) into an additional component based on the logical levels of the outputs of the phase detector, the CLK and CLK⬲ to be provided at least indirectly from a delay line that is at least indirectly in communication with the phase detector;the timing characteristics the timing characteristics to include a period of CIN defined as tck and a period from a rising edge in CIN to a rising edge in CKFB defined as te, anda first phase is when te>tck/2;a second phase is when te<tck/2;a third phase is when te=tck; anda fourth phase is when te=tck/2.

A method of improving efficiency of a delay-locked loop (DLL), comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB);detecting four or more timing conditions based upon phases of CIN and CKFB; andselectively inputting a clock signal (CLK) or inverted clock signal (CLK⬲) from a dealy line into a clock tree driver (CTD) based on the detected timing condition to reduce a number of effective delay stages in the DLL.

A method of improving efficiency of a delay-locked loop (DLL), comprising:nproviding a clock input signal CIN, and clock feedback signal (CKFB), each signal having timing characteristics;interposing a phase detector and selection system between an external clock signal and a clock tree driver (CTD) wherein the selection system is interposed between the clock tree driver (CTD) and delay Line;selecting a clock tree driver input based on a delay line output and at least one output of the phase detector; andselectively directing the signals based upon the phase of the signals.

A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB), each signal having timing characteristics;differentiating, with a phase detector, four or more phases based upon the timing characteristics of CIN and CKFB; andselecting a delay line output; based on the phases, the delay line output is selected from one of a clock signal (CLK) or inverted clock signal (CLK⬲) to be input into a clock tree driver (CTD), thereby reducing a number of effective delay stages in the DLL.

A method of reducing a number of effective delay stages in a delay-locked loop (DLL), comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB), each signal having timing characteristics;determining four or more phases based upon the timing characteristics of CIN and CKFB; andfor at least one phase, directing a clock signal (CLK) into a clock tree driver (CTD) such that a reduced number of delay stages is achieved, wherein a delay line is configured to output the CLK based on the plurality of phases.

A circuit for use with an external clock signal, comprising:nan input buffer comprising an input connected to an external clock signal and an output connected to a clock input signal (CIN) for comparison with a clock feedback signal (CKFB), each signal comprising timing characteristics; anda phase detector disposed between the input buffer and an output buffer, the phase detector comprising a first input to receive the CIN, a second input to receive the CKFB, and the phase detector to generate one of four or more output signal combinations, each combination corresponding to a phase of the signals based on the timing characteristics;the circuit comprising a delay line input, a selection multiplexor connected to the delay line input, a clock tree driver (CTD) to receive an output of the selection multiplexor, and a feedback loop to connect CKFB to the phase detector, and the circuit to selectively input a clock signal (CLK) or inverted clock signal (CLK⬲) as an input based on the phase of the signals, to reduce a number of effective delay stages for at least one of the phases.

A synchronous dynamic random access memory (SDRAM), comprising:na delay-locked loop (DLL), comprising:a phase detection system, comprising:a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector comprising a pair of registers, the registers comprising a pair of inputs and a pair of outputs, each of the outputs comprising a logical level, the logical levels to define a plurality of output signal combinations, each of the output signal combinations representative of a phase based upon the timing characteristics of the CIN and CKFB, and at least one of the phases reduces a lock period of the CIN when input into the DLL to achieve locking with an external clock signal with respect to another phase; andan input selection multiplexor to select either an input clock signal (CLK) or an inverted clock signal (CLK⬲) into a clock tree driver (CTD) based on the logical levels of the outputs of the phase detector, the CLK and CLK⬲ to be provided at least indirectly from a delay line;the timing characteristics to include a period of CIN defined as tck and a period from a rising edge in CIN to a rising edge in CKFB defined as te; anda first phase is when te>tck/2; anda second phase is when te<tck/2; anda third phase is when te=tck; anda fourth phase is when te=tck/2.

A method of improving efficiency of a delay-locked loop (DLL) comprising:nproviding a clock input signal (CIN) and a clock feedback signal (CKFB);detecting four or more timing conditions based upon phases of CIN and CKFB; andselectively inputting a clock signal (CLK) or inverted clock signal (CLK⬲) into a clock tree driver (CTD) based on the detected timing condition to reduce a number of effective delay stages in the DLL, wherein a single phase detector detects the timing conditions, wherein a delay line is interposed between the phase detector and a multiplexor, and the multiplexor is interposed between the CTD and the delay line.