Inventor
Hui-Zhong Zhuang
Inventor
Kaohsiung, TW
Overview
Patents· 97 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H01LSemiconductor devices25%
G06FElectric digital data processing20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H03KPulse technique5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
G01RMeasuring electric variables1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H10BElectronic memory devices1%
PatentTitleYear
11,126,775IC layout, method, device, and system202111,107,805Integrated circuit202111,100,273Integrated circuit and method of manufacturing same202111,093,684Power rail with non-linear edge202111,088,067Semiconductor device and layout design thereof202111,080,461Method for improved cut metal patterning202111,075,164Semiconductor device including a conductive feature over an active region202111,063,045Semiconductor device and method of manufacturing the same202111,048,849Integrated circuit and method of manufacturing the same202111,050,415Flip-flop with delineated layout for reduced footprint202111,037,957Semiconductor structure202111,030,368Metal cut optimization for standard cells202111,031,334Semiconductor device including a conductive feature over an active region202111,024,622Integrated circuit having angled conductive feature202111,004,855Buried metal track and methods forming same202110,971,586Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same202110,970,451Integrated circuit layout method, device, and system202110,970,440Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells202110,950,594Integrated circuit and method of fabricating the same202110,943,050Capacitive isolation structure insert for reversed signals202110,885,254Integrated circuit and method of manufacturing same202110,879,229Integrated circuit, system for and method of forming an integrated circuit202010,867,104Isolation circuit between power domains202010,867,100Integrated circuit designing system202010,867,114Integrated circuit and method of forming an integrated circuit202010,867,986Semiconductor device having fin structure202010,868,008Double rule integrated circuit layouts for a dual transmission gate202010,867,099System for designing integrated circuit layout and method of making the integrated circuit layout202010,854,499Integrated circuit, system for and method of forming an integrated circuit202010,797,078Hybrid fin field-effect transistor cell structures and related methods202010,783,313Method for improved cut metal patterning202010,740,531Integrated circuit, system for and method of forming an integrated circuit202010,734,321Integrated circuit and method of manufacturing same202010,734,377Integrated circuit, system for and method of forming an integrated circuit202010,727,177Semiconductor device and layout design thereof202010,707,199Integrated circuit layout and method of configuring the same202010,691,849Metal cut optimization for standard cells202010,685,162Layout for integrated circuit and the integrated circuit202010,685,982Semiconductor structure202010,678,977Semiconductor device having engineering change order (ECO) cells202010,664,639Cell layout and structure202010,553,575Semiconductor device having engineering change order (ECO) cells and method of using202010,530,345Flip-flop with delineated layout for reduced footprint202010,522,527System and method of processing cutting layout and example switching circuit201910,522,542Double rule integrated circuit layouts for a dual transmission gate201910,503,863Integrated circuit and method of manufacturing same201910,504,837Semiconductor device including a conductive feature over an active region201910,446,555Buried metal track and methods forming same201910,380,315Integrated circuit and method of forming an integrated circuit201910,380,306Layout of standard cells for predetermined function in integrated circuits201910,331,838Semiconductor device with fill cells201910,325,900Integrated circuit and method of fabricating the same201910,296,694Integrated circuit and method of manufacturing same201910,289,789System for designing integrated circuit layout and method of making the integrated circuit layout201910,277,227Semiconductor device layout201910,270,432Flip-flop with delineated layout for reduced footprint201910,269,784Integrated circuit layout and method of configuring the same201910,163,883Layout method for integrated circuit and layout of the integrated circuit201810,163,880Integrated circuit and method of fabricating the same201810,157,902Semiconductor devices with cells comprising routing resources201810,157,910Circuits and structures including tap cells and fabrication methods thereof201810,141,256Semiconductor device and layout design thereof201810,127,340Standard cell layout, semiconductor device having engineering change order (ECO) cells and method20189,991,158Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device20189,984,191Cell layout and structure20189,899,263'Method of forming layout design'20189,846,757Cell grid architecture for FinFET technology20179,831,230Standard cell layout, semiconductor device having engineering change order (ECO) cells and method20179,806,071'Integrated circuit with elongated coupling'20179,767,243'System and method of layout design for integrated circuits'20179,691,666'Layout architecture for performance improvement'20179,679,915'Integrated circuit with well and substrate contacts'20179,659,129'Standard cell having cell height being non-integral multiple of nominal minimum pitch'20179,653,393'Method and layout of an integrated circuit'20179,641,161'Flip-flop with delineated layout for reduced footprint'20179,626,472'Method and system of forming layout design'20179,536,032'Method and system of layout placement based on multilayer gridlines'20179,501,600'Standard cells for predetermined function having different types of layout'20169,431,381'System and method of processing cutting layout and example switching circuit'20169,425,141'Integrated circuit with elongated coupling'20169,412,700'Semiconductor device and method of manufacturing semiconductor device'20169,336,348'Method of forming layout design'20169,337,290'Layout architecture for performance improvement'20169,317,646'Masks formed based on integrated circuit layout design having cell that includes extended active region'20169,245,887'Method and layout of an integrated circuit'20169,213,795'Multiple via connections using connectivity rings'20159,202,696'Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits'20159,158,877'Standard cell metal structure directly over polysilicon structure'20159,123,565'Masks formed based on integrated circuit layout design having standard cell that includes extended active region'20159,105,466'Integrated circuit'20159,098,668'Layout of an integrated circuit'20159,087,170'Cell layout design and method'20158,872,269'Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits'20148,813,016'Multiple via connections using connectivity rings'20148,756,552'Multiple via connections using connectivity rings'20148,607,172'Integrated circuits and methods of designing the same'20138,482,314'Method and apparatus for improved multiplexing using tri-state inverter'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (13)· patent assignee history
2013–2016Patents assigned to Zhuang hui-zhong (4)· patent assignee history
2013–2014Patents assigned to CHEN CHUN-FU (2)· patent assignee history
2013–2016Patents assigned to LU LEE-CHUNG (2)· patent assignee history
2013–2021Based in Kaohsiung, TW· patent location history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (83)· patent assignee history
2017–2020Based in Kaohisung, TW· patent location history
2018Based in Kaoshung, TW· patent location history
2019–2020Based in Kaohsiun, TW· patent location history
2021Based in Tainan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 83 | 2015–2021 |
| TAIWAN SEMICONDUCTOR MFG | 13 | 2013–2016 |
| Zhuang hui-zhongself | 4 | 2013–2016 |
| CHEN CHUN-FU | 2 | 2013–2014 |
| LU LEE-CHUNG | 2 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 91 | 2013–2021 |
| Kaohsiun, TW | 2 | 2019–2020 |
| Kaohisung, TW | 2 | 2017–2020 |
| Tainan, TW | 1 | 2021 |
| Kaoshung, TW | 1 | 2018 |