A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

Claims

20 · 3 independent · depth 2

20 granted claims

›1.independentA semiconductor device comprising:na substrate having a first layer and a second layer;an extended drift region in the first layer, the extended drift…+7

›2.↳ 1The semiconductor device of claim 1, wherein the first conductivity type is an n-type conductivity, and the second conductivity type is a p-type condu…d2

›3.↳ 1The semiconductor device of claim 1, wherein the first conductivity type is a p-type conductivity, and the second conductivity type is an n-type condu…d2

›4.↳ 1The semiconductor device of claim 1, further comprising a field ring in the first region.d2

›5.↳ 1The semiconductor device of claim 1, wherein the extended drift region and the first region have a combined thickness greater than about 8 μm.d2

›6.↳ 1The semiconductor device of claim 1, wherein the first field dielectric comprises shallow trench isolation.d2

›7.↳ 1The semiconductor device of claim 1, further comprising a plurality of partition regions located within the first region between and having the second…d2

›8.↳ 1The semiconductor device of claim 1, wherein the substrate, the extended drift region, and the first region have dimensions set according to the reduc…d2

›9.independentA lateral-diffused metal oxide semiconductor (LDMOS) device comprising:na substrate having a first layer and second layer, the first layer having an e…+7

›17.independentA lateral diffused superjunction metal oxide semiconductor (LPMOS) device comprising:na substrate having a first layer and second layer;an extended dr…+3

Classifications

3 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/78

USPC · US Patent Classification

257/339257/E29.258

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2.3 y

844 days filing → grant

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non-final + final

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2 RCE

Examiner

Chandra Chaudhari

art unit 2891 · TC 2800

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20090085101 A1	2 Apr 2009

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