LexDanaLexDanabeta
Inventor

Ajay V. Bhatt

Inventor
Portland, OR, US

Overview

43→
Patents
1997–2020
Patent span
Physics
Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing41%
H04LTransmission of digital information, e.g. telegraphic communication27%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use22%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
H04QSelecting2%
H01RElectrically-conductive connections1%
H04WWireless communication networks1%
PatentTitleYear
10,642,665Multimodal interface202010,585,721Multimodal interface20209,753,557'Fast inking a touch display'20179,535,838'Atomic operations in PCI express'20179,450,363'Modular power adaptor with a base modular unit having plurality of surface connectors for connection to a power source'20169,442,855'Transaction layer packet formatting'20169,098,415'PCI express transaction descriptor'20159,047,222'Unified multi-transport medium connector architecture'20159,032,105'Scalable method and apparatus to configure a link'20159,032,103'Transaction re-ordering'20159,026,682'Prefectching in PCI express'20159,003,164'Providing hardware support for shared virtual memory between local and remote physical memory'20158,983,460'Sensor and context based adjustment of the operation of a network controller'20158,806,068'Transaction re-ordering'20148,793,404'Atomic operations'20148,719,547'Providing hardware support for shared virtual memory between local and remote physical memory'20148,700,821'Unified multi-transport medium connector architecture'20148,555,101'PCI express enhancements and extensions'20138,549,183'PCI express enhancements and extensions'20138,473,642'PCI express enhancements and extensions including device window caching'20138,447,888'PCI express enhancements and extensions'20138,407,367'Unified connector architecture'20138,296,469'Scalable method and apparatus for link with reconfigurable ports'20128,230,119'PCI express enhancements and extensions'20128,230,120'PCI express enhancements and extensions'20128,099,523'PCI express enhancements and extensions including transactions having prefetch parameters'20128,073,981'PCI express enhancements and extensions'20117,949,794'PCI express enhancements and extensions'20117,930,566'PCI express enhancements and extensions'20117,916,750'Transaction layer packet compression'20117,899,943'PCI express enhancements and extensions'20117,809,969'Using asymmetric lanes dynamically in a multi-lane serial link'20107,757,020'Point-to-point link negotiation method and apparatus'20107,633,877'Method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link'20095,909,556'M&A for exchanging date, status and commands over an hierarchical serial bus assembly using communication packets'19995,881,252'Method and apparatus for automatically configuring circuit cards in a computer system'19995,768,542'Method and apparatus for automatically configuring circuit cards in a computer system'19985,742,847'M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions'19985,708,849'Implementing scatter/gather operations in a direct memory access device on a personal computer'19985,694,555'Method and apparatus for exchanging data, status, and commands over an hierarchical serial bus assembly using communication packets'19975,655,127'Method and apparatus for control of power consumption in a computer system'19975,623,610'System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset'19975,615,404'System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2020Patents assigned to INTEL CORP (41)· patent assignee history
1997–1999Based in El Dorado Hills, CA, US· patent location history
1998Based in Beverly Hills, CA, US· patent location history
2009–2020Based in Portland, OR, US· patent location history
2011–2014Patents assigned to BHATT AJAY (10)· patent assignee history
2011–2014Patents assigned to SETHI PRASHANT (10)· patent assignee history
2011–2014Patents assigned to AJANOVIC JASMIN (9)· patent assignee history
2011–2014Patents assigned to AKIYAMA JAMES (9)· patent assignee history
2012–2014Based in Beaverton, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP411997–2020
BHATT AJAYself102011–2014
SETHI PRASHANT102011–2014
AJANOVIC JASMIN92011–2014
AKIYAMA JAMES92011–2014
Locations
LocationPatentsSpan
Portland, OR, US322009–2020
El Dorado Hills, California, US71997–1999
Beaverton, OR, US22012–2014
Beverly Hills, California, US21998