USPatentGranted
B2

Transaction re-ordering

Granted 12 Aug 2014 · 2 office actions

Assignee: Intel Corporation

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Inventors: Mark B. Rosenbluth, Mahesh Wagh, Ohad Falik, Prashant Sethi +15 · Examiner: Idriss N Alrobaye · AU 2181 · TC 2100

Life of the patent

12 dated events
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Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

27 · 5 independent · depth 3
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27 granted claims

Classifications

5 codes
IPC · International Patent Classification
Section G — Physics
  • G06F3/00
  • G06F5/00
USPC · US Patent Classification
710/5710/40710/36

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File wrapper

⤢ drag to zoomJan 2013Apr 2013Jul 2013Oct 2013Jan 2014Apr 2014Jul 2014Oct 2014USPTOApplicantNon-final rejectionResponse after non-finalRequest for continued examinationRequest for continued examination
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Pendency
1.7 y
614 days filing → grant
Office actions
1
non-final + final
Responses
1
2 RCE
Interviews
1
examiner interview summaries
Examiner
Idriss N Alrobaye
art unit 2181 · TC 2100
Citations: 135 back · 1 forward

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Term & fees

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Priority chain

1 priority documents
›Priority documents — 1
TypeDocumentDate
related publicationUS 20130097353 A118 Apr 2013

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Citations

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