Transaction re-ordering
Granted 12 Aug 2014 · 2 office actions
Assignee: Intel Corporation
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Attorney: Attorney · Log in to unlock
Inventors: Mark B. Rosenbluth, Mahesh Wagh, Ohad Falik, Prashant Sethi +15 · Examiner: Idriss N Alrobaye · AU 2181 · TC 2100
Life of the patent
12 dated eventsAbstract
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Claims
27 · 5 independent · depth 3Classifications
5 codes- G06F3/00
- G06F5/00
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1 priority documents›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| related publication | US 20130097353 A1 | 18 Apr 2013 |
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