Inventor

Thomas Andrew Sartorius

Inventor

Raleigh, NC, US

Overview

1994–2021

Patent span

Physics

Primary field (CPC G)

Patents· 108 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing79%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use15%

H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light2%

B64CAeroplanes1%

B64DEquipment for fitting in or to aircraft1%

B64UUnmanned aerial vehicles [uav]1%

G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein1%

G06TImage data processing or generation, in general1%

PatentTitleYear

11,126,437Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data2021 11,014,666Airframe2021 10,114,756Externally programmable memory management unit2018 9,847,615Method and arrangement for spectral broadening of laser pulses for non-linear pulse compression2017 9,710,269'Early conditional selection of an operand'2017 9,606,818'Systems and methods of executing multiple hypervisors using multiple sets of processors'2017 9,514,061'Method and apparatus for cache tag compression'2016 9,484,705'Optically end-pumped slab amplifier comprising pump modules arranged in a distributed manner'2016 9,471,325'Method and apparatus for selective renaming in a microprocessor'2016 9,436,616'Multi-core page table sets of attribute fields'2016 9,292,442'Methods and apparatus for improving performance of semaphore management sequences across a coherent bus'2016 9,092,358'Memory management unit with pre-filling capability'2015 9,086,813'Method and apparatus to save and restore system memory management unit (MMU) contexts'2015 9,063,749'Hardware support for hashtables in dynamic languages'2015 9,026,744'Enforcing strongly-ordered requests in a weakly-ordered processing'2015 9,026,681'Flexible hardware module assignment for enhanced performance'2015 8,943,300'Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information'2015 8,938,602'Multiple sets of attribute fields within a single page table entry'2015 8,924,685'Configuring surrogate memory accessing agents using non-priviledged processes'2014 8,880,860'Methods and apparatus for saving conditions prior to a reset for post reset evaluation'2014 8,782,356'Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions'2014 8,661,229'Power efficient instruction prefetch mechanism'2014 8,639,943'Methods and systems for checking run-time integrity of secure code cross-reference to related applications'2014 8,527,713'Cache locking without interference from normal allocations'2013 8,386,716'Apparatus and methods to reduce castouts in a multi-level cache hierarchy'2013 8,352,713'Debug circuit comparing processor instruction set operating mode'2013 8,352,682'Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system'2013 8,239,657'Address translation method and apparatus'2012 8,145,883'Preloading instructions from an instruction set other than a currently executing instruction set'2012 8,082,428'Methods and system for resolving simultaneous predicted branch instructions'2011 8,078,803'Apparatus and methods to reduce castouts in a multi-level cache hierarchy'2011 7,996,616'Apparatus and methods to reduce castouts in a multi-level cache hierarchy'2011 7,984,279'System and method for using a working global history register'2011 7,949,861'Method and apparatus for managing instruction flushing in a microprocessor\'s instruction pipeline'2011 7,917,731'Method and apparatus for prefetching non-sequential instruction addresses'2011 7,827,392'Sliding-window, block-based branch target address cache'2010 7,805,588'Caching memory attribute indicators with cached memory data field'2010 7,802,055'Virtually-tagged instruction cache with physically-tagged behavior'2010 7,725,684'Speculative instruction issue in a simultaneously multithreaded processor'2010 7,725,625'Latency insensitive FIFO signaling protocol'2010 7,721,067'Translation lookaside buffer manipulation'2010 7,711,927'System, method and software to preload instructions from an instruction set other than one currently executing'2010 7,698,536'Method and system for providing an energy efficient register file'2010 7,685,373'Selective snooping by snoop masters to locate updated data'2010 7,681,022'Efficient interrupt return address save mechanism'2010 7,676,659'System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding'2010 7,669,039'Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction'2010 7,650,466'Method and apparatus for managing cache partitioning using a dynamic boundary'2010 7,624,256'System and method wherein conditional instructions unconditionally provide output'2009 7,624,254'Segmented pipeline flushing for mispredicted branches'2009 7,617,387'Methods and system for resolving simultaneous predicted branch instructions'2009 7,610,463'Method and apparatus for performing an atomic semaphore operation'2009 7,587,580'Power efficient instruction prefetch mechanism'2009 7,568,070'Instruction cache having fixed number of variable length instructions'2009 7,552,283'Efficient memory hierarchy management'2009 7,500,045'Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system'2009 7,478,228'Apparatus for generating return address predictions for implicit and explicit subroutine calls'2009 7,454,538'Latency insensitive FIFO signaling protocol'2008 7,437,537'Methods and apparatus for predicting unaligned memory access'2008 7,426,626'TLB lock indicator'2008 7,424,563'Two-level interrupt service routine'2008 7,421,529'Method and apparatus to clear semaphore reservation for exclusive access to shared memory'2008 7,421,568'Power saving methods and apparatus to selectively enable cache bits based on known processor state'2008 7,415,638'Pre-decode error handling via branch correction'2008 7,406,613'Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions'2008 7,404,042'Handling cache miss in an instruction crossing a cache line boundary'2008 7,395,380'Selective snooping by snoop masters to locate updated data'2008 7,376,815'Methods and apparatus to insure correct predecode'2008 7,366,877'Speculative instruction issue in a simultaneously multithreaded processor'2008 7,366,869'Method and system for optimizing translation lookaside buffer entries'2008 7,330,941'Global modified indicator to reduce power consumption on cache miss'2008 7,296,175'System on a chip bus with automatic pipeline stage insertion for timing closure'2007 7,281,118'Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor'2007 7,278,012'Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions'2007 7,263,577'Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state'2007 7,210,024'Conditional instruction execution via emissary instruction for condition evaluation'2007 7,203,826'Method and apparatus for managing a return stack'2007 7,152,155'System and method of correcting a branch misprediction'2006 7,127,562'Ensuring orderly forward progress in granting snoop castout requests'2006 7,093,058'Single request data transfer regardless of size and alignment'2006 7,093,100'Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes'2006 7,089,376'Reducing snoop response time for snoopers without copies of requested data via snoop filtering'2006 7,035,958'Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target'2006 6,993,619'Single request data transfer regardless of size and alignment'2006 6,985,972'Dynamic cache coherency snooper presence with variable snoop latency'2006 6,976,132'Reducing latency of a snoop tenure'2005 6,970,962'Transfer request pipeline throttling'2005 6,948,053'Efficiently calculating a branch target address'2005 6,907,502'Method for moving snoop pushes to the front of a request queue'2005 6,834,378'System on a chip bus with automatic pipeline stage insertion for timing closure'2004 6,826,747'System and method for tracing program instructions before and after a trace triggering event within a processor'2004 6,826,656'Reducing power in a snooping cache based multiprocessor environment'2004 6,816,962'Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions'2004 6,807,608'Multiprocessor environment supporting variable-sized coherency transactions'2004 6,560,677'Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory'2003 6,513,134'System and method for tracing program execution within a superscalar processor'2003 6,504,854'Multiple frequency communications'2003 6,081,860'Address pipelining for data transfers'2000 5,996,092'System and method for tracing program execution within a processor before and after a triggering event'1999 5,925,118'Methods and architectures for overlapped read and write operations'1999 5,926,831'Methods and apparatus for control of speculative memory accesses'1999 5,910,930'Dynamic control of power management circuitry'1999 5,862,353'Systems and methods for dynamically controlling a bus'1999 5,848,436'Method and apparatus for efficiently providing data from a data storage medium to a processing entity'1998 5,809,293'System and method for program execution tracing within an integrated processor'1998 5,724,572'Method and apparatus for processing null terminated character strings'1998 5,371,872'Method and apparatus for controlling operation of a cache memory during an interrupt'1994 5,367,653'Reconfigurable multi-way associative cache memory'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2010Patents assigned to IBM (36)· patent assignee history

1994–2021Based in Raleigh, NC, US· patent location history

2006–2018Patents assigned to QUALCOMM INC (67)· patent assignee history

2011–2017Patents assigned to SARTORIUS THOMAS ANDREW (18)· patent assignee history

2011–2017Patents assigned to DIEFFENDERFER JAMES NORRIS (11)· patent assignee history

2011–2015Patents assigned to SMITH RODNEY WAYNE (5)· patent assignee history

2014Based in San Diego, CA, US· patent location history

2016–2017Based in Aachen, DE· patent location history

2021Based in Los Angeles, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
QUALCOMM INC	67	2006–2018
IBM	36	1994–2010
SARTORIUS THOMAS ANDREWself	18	2011–2017
DIEFFENDERFER JAMES NORRIS	11	2011–2017
SMITH RODNEY WAYNE	5	2011–2015

Locations

Location	Patents	Span
Raleigh, NC, US	104	1994–2021
Aachen, DE	2	2016–2017
Los Angeles, California, US	1	2021
San Diego, California, US	1	2014