Inventor
Hoi-Sung Chung
Inventor
Hwaseong-si, KR
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices34%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H01LSemiconductor devices25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10BElectronic memory devices5%
H02JElectric power networks1%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
H04BTransmission1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,938,243Power transmission apparatus and power transmission method202110,297,601Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same20199,985,036Semiconductor device having embedded strain-inducing pattern and method of forming the same20189,768,300'Semiconductor devices including a stressor in a recess and methods of forming the same'20179,741,855'Semiconductor devices including a stressor in a recess and methods of forming the same'20179,640,658'Semiconductor devices and methods of fabricating the same'20179,548,301'Semiconductor devices including a stressor in a recess and methods of forming the same'20179,537,009'Semiconductor devices including a stressor in a recess and methods of forming the same'20179,520,497'Semiconductor devices including a stressor in a recess and methods of forming the same'20169,502,563'Semiconductor device having embedded strain-inducing pattern and method of forming the same'20169,397,216'Semiconductor devices including a stressor in a recess and methods of forming the same'20169,324,834'Semiconductor device having embedded strain-inducing pattern and method of forming the same'20169,299,836'Semiconductor devices including multilayer source/drain stressors and methods of manufacturing the same'20169,257,520'Semiconductor devices including a stressor in a recess and methods of forming the same'20169,236,475'Semiconductor devices and methods of fabricating the same'20169,214,530'Methods of forming semiconductor devices including a stressor in a recess'20159,178,060'Semiconductor devices and methods of fabricating the same'20159,136,176'Semiconductor devices including an epitaxial layer with a slanted surface'20159,129,952'Semiconductor devices including a stressor in a recess and methods of forming the same'20159,082,874'Semiconductor device including transistor and method of manufacturing the same'20159,023,718'Method of fabricating semiconductor device'20159,024,385'Semiconductor devices including a stressor in a recess and methods of forming the same'20158,937,343'Semiconductor device including transistor and method of manufacturing the same'20158,921,192'Semiconductor devices and methods of fabricating the same'20148,907,426'Semiconductor device having embedded strain-inducing pattern and method of forming the same'20148,900,942'Semiconductor devices and methods of fabricating the same'20148,703,592'Methods of forming semiconductor devices having faceted semiconductor patterns'20148,673,747'Method of fabricating semiconductor device'20148,648,424'Semiconductor device including transistors having embedded source/drain regions each including upper and lower main layers comprising germanium'20148,637,373'Transistors and methods of manufacturing the same'20148,575,705'Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same'20138,551,846'Methods for fabricating semiconductor devices'20138,450,125'Methods of evaluating epitaxial growth and methods of forming an epitaxial layer'20138,426,926'Semiconductor devices having field effect transistors with epitaxial patterns in recessed regions'20138,207,040'Methods of manufacturing semiconductor devices including forming (111) facets in silicon capping layers on source/drain regions'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (34)· patent assignee history
2012–2017Patents assigned to CHUNG HOI-SUNG (12)· patent assignee history
2012–2017Patents assigned to SHIN DONG-SUK (11)· patent assignee history
2012–2018Based in Hwaseong-si, KR· patent location history
2013–2016Patents assigned to CHUNG HOI SUNG (6)· patent assignee history
2013–2016Patents assigned to KIM MYUNGSUN (6)· patent assignee history
2016–2019Based in Suwon-si, KR· patent location history
2021Based in Gyeonggi-do, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 34 | 2012–2021 |
| CHUNG HOI-SUNGself | 12 | 2012–2017 |
| SHIN DONG-SUK | 11 | 2012–2017 |
| CHUNG HOI SUNGself | 6 | 2013–2016 |
| KIM MYUNGSUN | 6 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hwaseong-si, KR | 30 | 2012–2018 |
| Suwon-si, KR | 4 | 2016–2019 |
| Gyeonggi-do, KR | 1 | 2021 |