Semiconductor devices including a stressor in a recess and methods of forming the same

A semiconductor device, comprising:na substrate comprising an active region;a gate electrode on the active region;a trench in the active region adjacent a side of the gate electrode, wherein the trench comprises a notched portion of the active region;an embedded stressor in the trench,wherein the embedded stressor comprises a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer,wherein the upper semiconductor layer comprises a first width narrower than a second width of the lower semiconductor layer, and alignment of a side surface of the upper semiconductor layer is offset from an outer side surface of the lower semiconductor layer, andwherein an uppermost surface of the upper semiconductor layer is higher than an uppermost surface of the active region; anda spacer between the upper semiconductor layer and the gate electrode, wherein the lower semiconductor layer contacts both a side and a bottom of the spacer and the upper semiconductor layer is spaced apart from the spacer.

A semiconductor device, comprising:na substrate comprising first and second regions, wherein the first and second regions comprise different respective pattern densities;a first gate electrode on a first active region in the first region;a first spacer on a side of the first gate electrode;a first additional spacer on the first spacer;a first trench in the first active region adjacent the side of the first gate electrode;a first embedded stressor in the first trench;a second gate electrode on a second active region in the second region;a second spacer on a side of the second gate electrode;a second additional spacer on the second spacer;a second trench in the second active region adjacent the side of the second gate electrode; anda second embedded stressor in the second trench,wherein the first embedded stressor comprises a first upper semiconductor layer and a first lower semiconductor layer between a surface of the first trench and the first upper semiconductor layer,wherein a lowermost portion of the first upper semiconductor layer is lower than an uppermost surface of the first lower semiconductor layer,wherein the second embedded stressor comprises a second upper semiconductor layer and a second lower semiconductor layer between a surface of the second trench and the second upper semiconductor layer, andwherein the first upper semiconductor layer has a first thickness greater than a second thickness of the second upper semiconductor layer.

A semiconductor device, comprising:nan active region in a substrate;a gate structure comprising a gate electrode on the active region;a cavity in the active region adjacent a side of the gate electrode, wherein the cavity comprises a notched portion of the active region; anda stressor comprising a lower layer at least partially in the cavity and an upper layer on the lower layer,wherein the lower layer contacts both a lower surface and a side of the gate structure,the upper layer is spaced apart from the gate structure,an uppermost surface of the lower layer is higher than an uppermost surface of the active region, andan uppermost surface of the upper layer is higher than the uppermost surface of the active region and the upper layer exposes portions of the lower layer adjacent opposing sidewalls of the upper layer when viewed in cross section.