Inventor

Joseph E. Geusic

Inventor

Berkeley Heights, NJ, US

Overview

1982–2013

Patent span

Electricity

Primary field (CPC H)

Patents· 93 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

H10DInorganic electric semiconductor devices13%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

G02BOptical elements, systems or apparatus10%

B82YSpecific uses or applications of nanostructures9%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H10BElectronic memory devices7%

G11CStatic stores5%

H05KPrinted circuits4%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%

PatentTitleYear

8,470,687'Strained semiconductor by full wafer bonding'2013 7,994,595'Strained semiconductor by full wafer bonding'2011 7,989,311'Strained semiconductor by full wafer bonding'2011 7,964,124'Method of forming cellular material'2011 7,564,082'Gettering using voids formed by surface transformation'2009 7,550,824'Low k interconnect dielectric using surface transformation'2009 7,547,954'Electronic systems using optical waveguide interconnects formed through a semiconductor wafer'2009 7,544,984'Gettering using voids formed by surface transformation'2009 7,512,170'Method of forming mirrors by surface transformation of empty spaces in solid state materials'2009 7,492,042'Integrated circuit cooling and insulating device and method'2009 7,485,497'Integrated circuit cooling and insulating device and method'2009 7,439,158'Strained semiconductor by full wafer bonding'2008 7,408,216'Device, system, and method for a trench capacitor having micro-roughened semiconductor surfaces'2008 7,326,597'Gettering using voids formed by surface transformation'2008 7,304,380'Integrated circuit cooling and insulating device and method'2007 7,300,821'Integrated circuit cooling and insulating device and method'2007 7,260,125'Method of forming mirrors by surface transformation of empty spaces in solid state materials'2007 7,242,049'Memory device'2007 7,196,929'Method for operating a memory device having an amorphous silicon carbide gate insulator'2007 7,169,666'Method of forming a device having a gate with a selected electron affinity'2007 7,164,156'Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer'2007 7,164,188'Buried conductor patterns formed by surface transformation of empty spaces in solid state materials'2007 7,153,775'Conductive material patterning methods'2006 7,154,153'Memory device'2006 7,142,577'Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon'2006 7,132,348'Low k interconnect dielectric using surface transformation'2006 7,109,548'Operating a memory device'2006 7,084,451'Circuits with a trench capacitor having micro-roughened semiconductor surfaces'2006 7,084,067'Removal of copper oxides from integrated interconnects'2006 7,054,532'Three-dimensional photonic crystal waveguide structure and method'2006 7,025,646'Microcavity discharge device'2006 7,022,604'Method of forming spatial regions of a second material in a first material'2006 7,018,467'Three-dimensional complete bandgap photonic crystal formed by crystal modification'2006 6,998,787'Method of operating a microcavity discharge device'2006 6,995,441'Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same'2006 6,995,443'Integrated circuits using optical fiber interconnects formed through a semiconductor wafer'2006 6,979,880'Scalable high performance antifuse structure and process'2005 6,972,257'Conductive material patterning methods'2005 6,950,585'Hollow core photonic bandgap optical fiber'2005 6,950,338'Method for operating a memory device having an amorphous silicon carbide gate insulator'2005 6,949,839'Aligned buried structures formed by surface transformation of empty spaces in solid state materials'2005 6,943,065'Scalable high performance antifuse structure and process'2005 6,929,984'Gettering using voids formed by surface transformation'2005 6,927,122'Method and structure for high capacitance memory cells'2005 6,909,113'Three-dimensional photonic band structures in solid materials'2005 6,898,362'Three-dimensional photonic crystal waveguide structure and method'2005 6,894,309'Spatial regions of a second material in a first material'2005 6,841,408'Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials'2005 6,829,421'Hollow core photonic bandgap optical fiber'2004 6,815,826'Alignment for buried structures formed by surface transformation of empty spaces in solid state materials'2004 6,812,513'Method and structure for high capacitance memory cells'2004 6,777,715'Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same'2004 6,723,577'Method of forming an optical fiber interconnect through a semiconductor wafer'2004 6,709,978'Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer'2004 6,706,597'Method for textured surfaces in floating gate tunneling oxide devices'2004 6,657,370'Microcavity discharge device'2003 6,630,713'Low temperature silicon wafer bond process with bulk material bond strength'2003 6,602,653'Conductive material patterning methods'2003 6,593,656'Multilevel copper interconnects for ultra large scale integration'2003 6,582,512'Method of forming three-dimensional photonic band structures in solid materials'2003 6,579,738'Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials'2003 6,579,803'Removal of copper oxides from integrated interconnects'2003 6,545,314'Memory using insulator traps'2003 6,526,191'Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same'2003 6,518,615'Method and structure for high capacitance memory cells'2003 6,496,370'Structure and method for an electronic assembly'2002 6,476,441'Method and structure for textured surfaces in floating gate tunneling oxide devices'2002 6,456,535'Dynamic flash memory cells with ultra thin tunnel oxides'2002 6,451,685'Method for multilevel copper interconnects for ultra large scale integration'2002 6,423,613'Low temperature silicon wafer bond process with bulk material bond strength'2002 6,383,924'Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials'2002 6,356,500'Reduced power DRAM device and method'2002 6,351,411'Memory using insulator traps'2002 6,348,125'Removal of copper oxides from integrated interconnects'2002 6,331,465'Alternate method and structure for improved floating gate tunneling devices using textured surface'2001 6,313,531'Coaxial integrated circuitry interconnect lines, and integrated circuitry'2001 6,309,907'Method of fabricating transistor with silicon oxycarbide gate'2001 6,294,813'Information handling system having improved floating gate tunneling devices'2001 6,249,460'Dynamic flash memory cells with ultrathin tunnel oxides'2001 6,246,606'Memory using insulator traps'2001 6,242,304'Method and structure for textured surfaces in floating gate tunneling oxide devices'2001 6,232,643'Memory using insulator traps'2001 6,219,237'Structure and method for an electronic assembly'2001 6,198,168'Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same'2001 6,150,188'Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same'2000 6,143,616'Methods of forming coaxial integrated circuitry interconnect lines'2000 6,140,181'Memory using insulator traps'2000 6,090,636'Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same'2000 6,025,627'Alternate method and structure for improved floating gate tunneling devices'2000 6,025,225'Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same'2000 5,981,350'Method for forming high capacitance memory cells'1999 5,886,368'Transistor with silicon oxycarbide gate and methods of fabrication and use'1999 4,334,291'Ion-implanted magnetic bubble memory with domain confinement rails'1982

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1982Patents assigned to BELL TELEPHONE LABOR INC (1)· patent assignee history

1982–2013Based in Berkeley Heights, NJ, US· patent location history

1999–2013Patents assigned to MICRON TECHNOLOGY INC (90)· patent assignee history

2013Patents assigned to AKRAM SALMAN (1)· patent assignee history

2013Patents assigned to FORBES LEONARD (1)· patent assignee history

2013Patents assigned to GEUSIC JOSEPH E (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	90	1999–2013
AKRAM SALMAN	1	2013
BELL TELEPHONE LABOR INC	1	1982
FORBES LEONARD	1	2013
GEUSIC JOSEPH Eself	1	2013

Locations

Location	Patents	Span
Berkeley Heights, New Jersey, US	93	1982–2013