USPatentGranted
B1

Method for operating a memory device having an amorphous silicon carbide gate insulator

Granted 27 Sep 2005 · 6 office actions

Application
9135413
filed 14 Aug 1998
Publication
Not published
not published
Patent· this page
US 6,950,338
granted 27 Sep 2005

Life of the patent

2 dated events
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Abstract

A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Claims

47 · 14 independent · depth 3
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47 granted claims

Classifications

6 codes
IPC · International Patent Classification
Section G — Physics
  • G11C016/04
USPC · US Patent Classification
365/185.14365/185.29257/77365/185.1257/316

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File wrapper

Pendency
7.1 y
2,601 days filing → grant
Office actions
3
after a restriction
Responses
5
11 RCE
Examiner
Viet Q. Nguyen
art unit 2818 · TC 2800
Citations: 247 back · 0 forward

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