Inventor
Michael D. Hutton
Inventor
Mountain View, CA, US
Overview
Patents· 107 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing43%
H03KPulse technique36%
G11CStatic stores5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H03MCoding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
H01LSemiconductor devices1%
H04QSelecting1%
H10DInorganic electric semiconductor devices1%
PatentTitleYear
10,678,979Method and apparatus for implementing a system-level design tool for design planning and architecture exploration202010,635,631Hybrid programmable many-core device with on-chip interconnect202010,523,207Programmable circuit having multiple sectors201910,515,165State visibility and manipulation in integrated circuits201910,367,756Programmable logic device with integrated network-on-chip201910,289,483Methods and apparatus for embedding an error correction code in storage circuits201910,248,484Prioritized error-detection and scheduling201910,127,190Hybrid programmable many-core device with on-chip interconnect201810,061,879Circuit design instrumentation for state visualization20189,983,990Configurable storage circuits with embedded processing and control circuitry20189,830,300Hybrid programmable many-core device with on-chip interconnect20179,798,842'Circuit design instrumentation for state visualization'20179,740,808'Method and apparatus for implementing a system-level design tool for design planning and architecture exploration'20179,705,506'Field programmable gate array with integrated application specific integrated circuit fabric'20179,697,318'State visibility and manipulation in integrated circuits'20179,588,176'Techniques for using scan storage circuits'20179,583,218'Configurable register circuitry for error detection and recovery'20179,575,862'Integrated circuits with error handling capabilities'20179,507,883'Method and apparatus for implementing a system-level design tool for design planning and architecture exploration'20169,478,272'Configurable storage blocks with embedded first-in first-out and last-in first-out circuitry'20169,479,456'Programmable logic device with integrated network-on-chip'20169,471,537'Hybrid programmable many-core device with on-chip interconnect'20169,471,388'Mapping network applications to a hybrid programmable many-core device'20169,450,609'Methods and apparatus for embedding an error correction code in memory cells'20169,292,474'Configurable hybrid adder circuitry'20169,294,092'Error resilient packaged components'20169,276,582'Method and circuit for scalable cross point switching using 3-D die stacking'20169,257,982'Error resilient packaged components'20169,251,300'Methods and tools for designing integrated circuits with auto-pipelining capabilities'20169,230,048'Integrated circuits with interconnect selection circuitry'20169,178,513'Memory blocks with shared address bus circuitry'20159,172,378'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers'20159,165,931'Apparatus for field-programmable gate array with configurable architecture and associated methods'20159,166,599'Methods and apparatus for building bus interconnection networks using programmable interconnection resources'20159,106,229'Programmable interposer circuitry'20159,077,338'Method and circuit for scalable cross point switching using 3-D die stacking'20159,053,274'Register retiming technique'20158,997,029'Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew'20158,860,458'Integrated circuits with logic regions having input and output bypass paths for accessing registers'20148,854,080'Integrated circuits with interconnect selection circuitry'20148,806,399'Register retiming technique'20148,704,548'Methods and apparatus for building bus interconnection networks using programmable interconnection resources'20148,640,067'Method and apparatus for implementing a field programmable gate array clock skew'20148,601,424'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers'20138,542,032'Integrated circuits with interconnect selection circuitry'20138,521,801'Configurable hybrid adder circuitry'20138,519,740'Integrated circuits with shared interconnect buses'20138,402,408'Register retiming technique'20138,381,142'Using a timing exception to postpone retiming'20138,314,636'Field programmable gate array with integrated application specific integrated circuit fabric'20128,185,854'Method and apparatus for performing parallel slack computation within a shared netlist region'20128,166,427'Tracing and reporting registers removed during synthesis'20128,112,728'Early timing estimation of timing statistical properties of placement'20128,108,812'Register retiming technique'20128,082,526'Dedicated crossbar and barrel shifter block on programmable logic resources'20118,072,238'Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions'20118,020,027'Timing control in a specialized processing block'20118,001,499'Circuit type pragma for computer aided design tools'20117,902,864'Heterogeneous labs'20117,890,910'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers'20117,839,165'User-accessible freeze-logic for dynamic power reduction and associated methods'20107,839,167'Interconnection and input/output resources for programmable logic integrated circuit devices'20107,827,433'Time-multiplexed routing for reducing pipelining registers'20107,818,705'Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew'20107,812,635'Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions'20107,804,325'Dedicated function block interfacing with general purpose function blocks on integrated circuits'20107,784,008'Performance visualization system'20107,733,124'Method and apparatus for PLD having shared storage elements'20107,724,032'Field programmable gate array with integrated application specific integrated circuit fabric'20107,716,623'Programmable logic device architectures and methods for implementing logic in those architectures'20107,705,628'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers'20107,689,955'Register retiming technique'20107,675,319'Programmable logic device having complex logic blocks with improved logic cell functionality'20107,671,625'Omnibus logic element'20107,619,443'Programmable logic device architectures and methods for implementing logic in those architectures'20097,605,603'User-accessible freeze-logic for dynamic power reduction and associated methods'20097,607,118'Techniques for using edge masks to perform timing analysis'20097,579,866'Programmable logic device with configurable override of region-wide signals'20097,577,929'Early timing estimation of timing statistical properties of placement'20097,545,196'Clock distribution for specialized processing block in programmable logic device'20097,509,618'Method and apparatus for facilitating an adaptive electronic design automation tool'20097,492,188'Interconnection and input/output resources for programmable logic integrated circuit devices'20097,469,394'Timing variation aware compilation'20087,420,390'Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size'20087,394,287'Programmable logic device having complex logic blocks with improved logic cell functionality'20087,373,631'Methods of producing application-specific integrated circuit equivalents of programmable logic'20087,368,944'Organizations of logic modules in programmable logic devices'20087,368,942'Dedicated resource interconnects'20087,355,442'Dedicated crossbar and barrel shifter block on programmable logic resources'20087,350,176'Techniques for mapping to a shared lookup table mask'20087,337,100'Physical resynthesis of a logic design'20087,330,052'Area efficient fractureable logic elements'20087,312,633'Programmable routing structures providing shorter timing delays for input/output signals'20077,248,072'Swap MUX to relieve logic device input line stress'20077,176,718'Organizations of logic modules in programmable logic devices'20077,135,888'Programmable routing structures providing shorter timing delays for input/output signals'20067,133,819'Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices'20067,120,883'Register retiming technique'20067,093,219'Techniques for using edge masks to perform timing analysis'20067,042,248'Dedicated crossbar and barrel shifter block on programmable logic resources'20067,010,777'Shared lookup table enhancements for the efficient implementation of barrel shifters'20066,989,689'Interconnection and input/output resources for programmable logic integrated circuit devices'20066,977,520'Time-multiplexed routing in a programmable logic device architecture'20056,894,533'Interconnection and input/output resources for programmable logic integrated circuit devices'20056,747,480'Programmable logic devices with bidirect ional cascades'20046,429,681'Programmable logic device routing architecture to facilitate register re-timing'20026,407,576'Interconnection and input/output resources for programmable logic integrated circuit devices'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2020Patents assigned to ALTERA CORP (105)· patent assignee history
2002–2020Based in Mountain View, CA, US· patent location history
2002–2020Based in Palo Alto, CA, US· patent location history
2009–2012Based in San Francisco, CA, US· patent location history
2011–2017Patents assigned to HUTTON MICHAEL D (16)· patent assignee history
2012–2013Patents assigned to VAN ANTWERPEN BABETTE (3)· patent assignee history
2012–2013Patents assigned to BAECKLER GREGG (2)· patent assignee history
2013–2015Patents assigned to LEWIS DAVID (3)· patent assignee history
2015–2016Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 105 | 2002–2020 |
| HUTTON MICHAEL Dself | 16 | 2011–2017 |
| LEWIS DAVID | 3 | 2013–2015 |
| VAN ANTWERPEN BABETTE | 3 | 2012–2013 |
| BAECKLER GREGG | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 92 | 2002–2020 |
| Palo Alto, California, US | 10 | 2002–2020 |
| San Jose, California, US | 3 | 2015–2016 |
| San Francisco, California, US | 2 | 2009–2012 |