A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.

Claims

19 · 3 independent · depth 7

19 granted claims

›1.independentCircuitry, comprising:nan interposer;a first circuit on the interposer that is characterized by a first reliability metric value; anda second circuit …+7

›2.↳ 1The circuitry defined in claim 1 wherein the second failure-in-time value of the second circuit is less than the first failure-in-time value of the fi…d2+6

›3.↳ 2The circuitry defined in claim 2 wherein the second circuit comprises a radiation-hardened circuit.d3+5

›9.independentA packaged component, comprising:nan interposer;first and second integrated circuits mounted on the interposer, wherein the second integrated circuit …+4

›14.independentA method of operating a packaged component including an integrated circuit mounted to an interposer, the method comprising:nwith radiation-hardened mo…+5

›15.↳ 14The method defined in claim 14 wherein configuring the integrated circuit with the test configuration comprises configuring at least a portion of the …d2

›16.↳ 14The method defined in claim 14 wherein configuring the integrated circuit with the test configuration comprises configuring the integrated circuit wit…d2

›17.↳ 14The method defined in claim 14 wherein the integrated circuit comprises programmable logic regions, wherein the integrated circuit has a configuration…d2

›18.↳ 14The method defined in claim 14, wherein monitoring the performance of the integrated circuit comprises:nwith a first trace buffer on the interposer, s…d2

›19.↳ 14The method defined in claim 14 further comprising:nwith the radiation-hardened monitor circuitry, monitoring temperature of the integrated circuit; an…d2

Classifications

2 codes

IPC · International Patent Classification

Section H — Electricity

H03K19/007
H03K19/003

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Jany Richardson

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Type	Document	Date
related publication	US 20150028918 A1	29 Jan 2015

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