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Inventor

Matthew Mattina

Inventor
Worcester, MA, US

Overview

48→
Patents
2005–2021
Patent span
Physics
Primary field (CPC G)

Patents· 48 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing61%
H04LTransmission of digital information, e.g. telegraphic communication22%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
G06NComputing arrangements based on specific computational models3%
G05FSystems for regulating electric or magnetic variables1%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
H01LSemiconductor devices1%
H03MCoding1%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
PatentTitleYear
11,120,101Matrix multiplication system and method202110,887,238High performance, scalable multi chip interconnect202110,747,845System, method and apparatus for computationally efficient data manipulation202010,606,750Computing in parallel processing environments202010,579,524Computing in parallel processing environments202010,515,045Computing in parallel processing environments201910,367,741High performance, scalable multi chip interconnect201910,339,059Global socket to socket cache coherence architecture201910,073,778Caching in multicore and multiprocessor architectures20189,886,275'Multi-core processor using three dimensional integration'20189,639,487'Managing cache memory in a parallel processing environment'20179,514,050'Caching in multicore and multiprocessor architectures'20169,507,745'Low latency dynamic route selection'20169,479,431'Route prediction in packet switched networks'20169,424,228'High performance, scalable multi chip interconnect'20169,298,618'Managing cache memory in a parallel processing environment'20169,135,215'Route prediction in packet switched networks'20158,934,347'Low latency dynamic route selection'20158,738,860'Computing in parallel processing environments'20148,677,081'Transferring and storing data in multicore and multiprocessor architectures'20148,631,205'Managing cache memory in a parallel processing environment'20148,572,353'Condensed router headers with low latency output port calculation'20138,560,780'Caching in multicore and multiprocessor architectures'20138,234,451'Caching in multicore and multiprocessor architectures'20128,209,490'Protocol for maintaining cache coherency in a CMP'20128,200,901'Managing cache memory in a parallel processing environment'20128,117,392'Method and apparatus for efficient ordered stores over an interconnection network'20128,112,581'Caching in multicore and multiprocessor architectures'20127,987,321'Caching in multicore and multiprocessor architectures'20117,882,307'Managing cache memory in a parallel processing environment'20117,853,752'Caching in multicore and multiprocessor architectures'20107,853,754'Caching in multicore and multiprocessor architectures'20107,853,755'Caching in multicore and multiprocessor architectures'20107,805,575'Caching in multicore and multiprocessor architectures'20107,805,577'Managing memory access in a parallel processing environment'20107,774,553'Caching in multicore and multiprocessor architectures'20107,747,897'Method and apparatus for lockstep processing on a fixed-latency interconnect'20107,733,898'Method and apparatus for preventing starvation in a slotted-ring network'20107,624,236'Predictive early write-back of owned cache blocks in a shared memory computer system'20097,620,954'Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors'20097,620,791'Mapping memory in a parallel processing environment'20097,558,920'Apparatus and method for partitioning a shared cache of a chip multi-processor'20097,551,564'Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect'20097,539,141'Method and apparatus for synchronous unbuffered flow control of packets on a ring interconnect'20097,461,210'Managing set associative cache memory according to entry type'20087,395,381'Method and an apparatus to reduce network utilization in a multiprocessor system'20087,240,186'System and method to avoid resource contention in the presence of exceptions'20076,925,552'Method and system with multiple exception handlers in a processor'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2009Based in Hudson, MA, US· patent location history
2008–2016Patents assigned to TILERA CORP (22)· patent assignee history
2008–2012Patents assigned to INTEL CORP (9)· patent assignee history
2008–2015Based in Worcester, MA, US· patent location history
2012–2019Patents assigned to MATTINA MATTHEW (19)· patent assignee history
2012–2016Patents assigned to AGARWAL ANANT (8)· patent assignee history
2013–2018Patents assigned to BRATT IAN RUDOLF (8)· patent assignee history
2013–2021Based in Boylston, MA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TILERA CORP222008–2016
MATTINA MATTHEWself192012–2019
INTEL CORP92008–2012
AGARWAL ANANT82012–2016
BRATT IAN RUDOLF82013–2018
Locations
LocationPatentsSpan
Worcester, Massachusetts, US252008–2015
Boylston, Massachusetts, US202013–2021
Hudson, Massachusetts, US32005–2009