USPatentGranted
B1Caching in multicore and multiprocessor architectures
Granted 10 Aug 2010 · 2 office actions
Current assignee: Mellanox Technologies Ltd. · originally Tilera Corporation
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Attorney: Attorney · Log in to unlock
Inventors: Matthew Mattina, Anant Agarwal, Ian R. Bratt · Examiner: Brian R Peugh · AU 2187 · TC 2100
Application
11/754,118
filed 25 May 2007
Publication
Not published
not published
Patent· this page
US 7,774,553
granted 10 Aug 2010
81
Claims
3 independent
73
File wrapper
transactions
2027
20-year term
term adjustment not held
none
Litigation
checked
2
Classifications
G06F12/00
62
Citations
61 cites · 1 cited by
Life of the patent
3 dated events⤢ drag to zoom
Prosecutionhover for detail · click to open
Abstract
A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.
Claims
81 · 3 independent · depth 681 granted claims
›1.independentA multicore processor comprising:na plurality of cache memories;a plurality of processor cores, each associated with one of the cache memories; anda p…+10
›2.↳ 1The processor of claim 1 embodied on a single integrated circuit.d2
›3.↳ 1The processor of claim 1 wherein the main memory is external to the multicore processor.d2
›4.↳ 1The processor of claim 1 wherein each of the memory interfaces includes storage for directory state.d2+3
›5.↳ 4The processor of claim 4 wherein the storage for the directory state includes a cache storage for the directory state.d3+2
›6.↳ 5The processor of claim 5 wherein maintaining the directory state includes processing memory access requests from the cache memories.d4
›7.↳ 5The processor of claim 5 wherein the cache storage for the directory state is associated with the main memory such that the directory state and data c…d4
›8.↳ 1The processor of claim 1 wherein the directory controllers are configured to maintain directory state associated with the corresponding portion of mai…d2
›9.↳ 1The processor of claim 1 wherein at least some of the directory controllers are associated with a processor core for processing a directory control pr…d2
›10.↳ 1The processor of claim 1 wherein the processor cores are interconnected over a network that includes at least one of: a bus, a ring, a mesh, a torus, …d2
›11.↳ 1The processor of claim 1 further comprising one or more input/output modules configured to couple data between a cache memory and an input/output inte…d2
›12.independentA method for managing cache memories associated with respective processor cores in a multicore processor that includes a plurality of memory interface…
›13.independentA multicore processor comprising:na plurality of cache memories;a plurality of processor cores, each associated with one of the cache memories; one or…+68
›14.↳ 13The processor of claim 13 wherein each of at least some of the processor cores includes a directory controller coupled to the associated cache memory.d2+35
›15.↳ 14The processor of claim 14 wherein each directory controller coupled to the associated cache memory is configured to maintain directory state associate…d3+9
›16.↳ 15The processor of claim 15 wherein the portion of the main memory that is cached in the associated cache memory comprises a set of memory lines having …d4+2
›17.↳ 16The processor of claim 16 wherein the addresses of the set of memory lines have one or more bits at specified positions in common.d5+1
›18.↳ 17The processor of claim 17 wherein the bits at the specified positions comprise low order bits.d6
›19.↳ 15The processor of claim 15 wherein each directory controller coupled to the associated cache memory is configured to maintain state to indicate whether…d4
›20.↳ 15The processor of claim 15 wherein each directory controller coupled to the associated cache memory is configured to maintain a read-only state in whic…d4
›21.↳ 15The processor of claim 15 wherein the processor core associated with the cache memory is coupled to a first network interconnecting the processor core…d4+3
›22.↳ 21The processor of claim 21 wherein the processor core is coupled to a third network interconnecting the processor cores for sending acknowledgements as…d5
›23.↳ 21The processor of claim 21 wherein the first and second networks each have an independent physical communication medium.d5
›24.↳ 21The processor of claim 21 wherein the first and second networks share a common physical communication medium, and each has independent buffer resource…d5
›25.↳ 14The processor of claim 14 wherein each of at least some of the cache memories is assigned as a home location for caching a corresponding portion of th…d3+13
›26.↳ 25The processor of claim 25, wherein the processor core associated with the cache memory is configured to manage the cache memory according to a level i…d4
›27.↳ 25The processor of claim 25 wherein the processor cores associated with the cache memory is configured to provide data requested in the memory request f…d4
›28.↳ 25The processor of claim 25 wherein the directory controller coupled to the cache memory is configured to implement a directory coherence protocol for t…d4+1
›29.↳ 28The processor of claim 28 wherein the directory coherence protocol implements a full map directory, a limited directory, a limitless directory, a coar…d5
›30.↳ 25The processor of claim 25 wherein the processor cores associated with respective cache memories are configured to reapportion directory state and rela…d4
›31.↳ 25The processor of claim 25 wherein the cache memory assigned as a home location is the same for memory lines corresponding to the same memory page in m…d4+2
›32.↳ 31The processor of claim 31 wherein each memory page is assigned a unique cache memory as a home location.d5+1
›33.↳ 32The processor of claim 32 wherein each memory page is assigned a coherence domain indicating which other cache memories are allowed to share the memor…d6
›34.↳ 25The processor of claim 25 wherein each processor core storing a memory line in its associated cache memory that is not assigned as the home location f…d4+1
›35.↳ 34The processor of claim 34 wherein the processor core whose associated cache memory is assigned as the home location of a given memory line is configur…d5
›36.↳ 25The processor of claim 25 wherein the cache memory assigned as a home location is assigned according to entries in a translation lookaside buffer.d4
›37.↳ 25The processor of claim 25 wherein the cache memory assigned as a home location is the same for memory lines whose addresses have one or more bits at s…d4+1
›38.↳ 37The processor of claim 37 wherein the bits at the specified positions comprise low order bits.d5
›39.↳ 14The processor of claim 14 wherein the directory controller coupled to the cache memory is implemented at least partially in software by interrupting a…d3
›40.↳ 14The processor of claim 14 wherein the processor core includes a first processor and a second processor configured to run protocol software to perform …d3
›41.↳ 14The processor of claim 14 wherein the directory controller coupled to the cache memory is configured to send an invalidate request to one or more proc…d3+5
›42.↳ 41The processor of claim 41 wherein the directory controller is further configured to maintain a count of outstanding acknowledgements to be received fr…d4
›43.↳ 41The processor of claim 41 wherein the directory controller is further configured to send the invalidate request in response to writing data in the cac…d4
›44.↳ 41The processor of claim 41 wherein the directory controller is further configured to send the invalidate request if a corresponding directory entry ind…d4+1
›45.↳ 44The processor of claim 44 wherein the invalidate request is sent to processor cores that share the cache line according to the directory entry.d5
›46.↳ 41The processor of claim 41 wherein the invalidate request in included in a message that is broadcast to multiple processor cores.d4
›47.↳ 14The processor of claim 14 wherein the directory controller coupled to the cache memory is configured to send an update request to one or more processo…d3
›48.↳ 14The processor of claim 14 wherein the directory controller coupled to the cache memory is configured to invalidate one or more cache lines in response…d3+1
›49.↳ 48The processor of claim 48 wherein the directory controller is further configured to respond to the message with an acknowledgement message sent over t…d4
›50.↳ 13The processor of claim 13 wherein each of at least some of the cache memories includes at least some of the storage for the directory state.d2+9
›51.↳ 50The processor of claim 50 wherein a directory entry stored in the storage for the directory state is associated with a cache line in the cache memory.d3+7
›52.↳ 51The processor of claim 51 wherein a directory entry is operated upon when a corresponding cache line is operated upon.d4+2
›53.↳ 52The processor of claim 52 wherein a directory entry is flushed when a corresponding cache line is flushed.d5+1
›54.↳ 53The processor of claim 53 wherein, when a directory entry stored on a given processor core is flushed, cached copies of data that are stored in cache …d6
›55.↳ 51The processor of claim 51 wherein each of at least some of the directory controllers is configured to switch a directory protocol mode during executio…d4+2
›56.↳ 55The processor of claim 55 wherein switching the directory protocol mode comprises switching between a mode in which copies of the cache line are inval…d5
›57.↳ 55The processor of claim 55 wherein switching the directory protocol mode comprises switching between a mode in which pointers associated with the cache…d5
›58.↳ 51The processor of claim 51 wherein the directory entry associated with the cache line includes state that indicates whether pointers associated with th…d4
›59.↳ 50The processor of claim 50 wherein the directory controllers are configured to store each of a linked sequence of pointers in multiple respective cache…d3
›60.↳ 13The processor of claim 13 wherein each of at least some of the memory interfaces includes a directory controller.d2+3
›61.↳ 60The processor of claim 60 wherein the directory controller is configured to handle a message including a memory access request received over a network…d3+2
›62.↳ 61The processor of claim 61 wherein the state information indicates whether cache coherence associated with the memory access request is handled by the …d4+1
›63.↳ 62The processor of claim 62 wherein each of at least some of the processor cores include at least some of the storage for directory state.d5
›64.↳ 13The processor of claim 13 wherein each of at least some of the memory interfaces includes at least some of the storage for directory state.d2+5
›65.↳ 64The processor of claim 64 wherein the storage for the directory state comprises a cache coupled to the memory interface.d3+4
›66.↳ 65The processor of claim 65 wherein each of at least some of the memory interfaces is configured to maintain a count of outstanding transactions associa…d4
›67.↳ 65The processor of claim 65 wherein the cache is a direct mapped cache, a fully associative cache, or a set associative cache.d4
›68.↳ 65The processor of claim 65 wherein the directory controllers are configured to handle a cache miss for a directory entry by fetching the directory entr…d4
›69.↳ 65The processor of claim 65 wherein the cache stores directory state and data associated with a cache line address.d4
›70.↳ 13The processor of claim 13 wherein each of at least some of the memory interfaces includes a memory controller that controls a portion of the main memo…d2+2
›71.↳ 70The processor of claim 70 wherein each memory controller is coupled to a port on the periphery of a network interconnecting the processor cores.d3+1
›72.↳ 71The processor of claim 71 wherein the memory interfaces are configured to translate network messages into a format that the memory controllers can use…d4
›73.↳ 13The processor of claim 13 wherein each of at least some of the processor cores includes a translation lookaside buffer to direct memory references to …d2
›74.↳ 13The processor of claim 13 wherein each portion of main memory is limited to being coherently cached in a respective set of one or more of the cache me…d2+5
›75.↳ 74The processor of claim 74 wherein a directory controller associated with one of the cache memories in a given set is configured to maintain state to i…d3+4
›76.↳ 75The processor of claim 75 wherein the directory controller is further configured to include an invalidate request in a message broadcast to multiple p…d4+3
›77.↳ 76The processor of claim 76, wherein the message is broadcast to the multiple processor cores using a tree pattern.d5
›78.↳ 76The processor of claim 76, wherein each of the multiple processor cores is configured to send an acknowledgement message in response to the message th…d5
›79.↳ 76The processor of claim 76, wherein the directory controller and each of the multiple processor cores are configured to communicate over a static netwo…d5
›80.↳ 13The processor of claim 13 wherein the processor cores are interconnected over a network that includes at least one of: a bus, a ring, a mesh, a torus,…d2
›81.↳ 13The processor of claim 13 further comprising one or more input/output modules configured to couple data between a cache memory and an input/output int…d2
Classifications
2 codesIPC · International Patent Classification
Section G — Physics
- G06F12/00
USPC · US Patent Classification
711/141
Claim changes
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File wrapper
Pendency
3.2 y
1,173 days filing → grant
Office actions
1
non-final + final
Responses
2
1 RCE
Examiner
Brian R Peugh
art unit 2187 · TC 2100
Law firm
Citations: 61 back · 1 forward
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1 priority documentsPriority
29 Sep 2006
earliest claimed
›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| provisional | US 60827473 00 | 29 Sep 2006 |
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