LexDanaLexDanabeta
Inventor

Pai-Hung Pan

Inventor
Boise, ID, US

Overview

115→
Patents
1986–2014
Patent span
Electricity
Primary field (CPC H)

Patents· 115 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices25%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
H10BElectronic memory devices11%
B24BMachines, devices, or processes for grinding or polishing2%
C23CCoating metallic material2%
H01LSemiconductor devices0%
Y10TTechnical subjects covered by former us classification0%
PatentTitleYear
8,790,982'Methods for reoxidizing an oxide and for fabricating semiconductor devices'20148,637,956'Semiconductor devices structures including an isolation structure'20148,492,851'Structures including an at least partially reoxidized oxide material'20138,338,264'Methods for forming isolation structures for semiconductor devices'20127,892,941'Technique for forming shallow trench isolation structure without corner exposure'20117,371,697'Ion-assisted oxidation methods and the resulting structures'20087,170,139'Semiconductor constructions'20077,132,035'Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes'20067,119,033'Ion-assisted oxidation methods and the resulting structures'20067,115,492'Technique for elimination of pitting on silicon substrate during gate stack etch using material in a non-annealed state'20067,078,342'Method of forming a gate stack'20067,049,664'Semiconductor device structures formed by ion-assisted oxidation'20067,041,548'Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof'20066,936,897'Intermediate structure having a silicon barrier layer encapsulating a semiconductor substrate'20056,888,212'Method for trench isolation by selective deposition of low temperature oxide films'20056,849,544'Forming a conductive structure in a semiconductor device'20056,844,252'Semiconductor processing methods of forming a conductive gate and line'20056,770,538'Ion-assisted oxidation methods and the resulting structures'20046,764,934'Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random'20046,753,243'SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY'20046,744,108'Doped silicon diffusion barrier region'20046,677,241'Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof'20046,660,180'Compositions for etching silicon with high selectivity to oxides and methods of using same'20036,645,865'Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes'20036,613,673'Technique for elimination of pitting on silicon substrate during gate stack etch'20036,613,675'Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes'20036,599,840'Material removal method for forming a structure'20036,596,648'Material removal method for forming a structure'20036,596,595'Forming a conductive structure in a semiconductor device'20036,596,642'Material removal method for forming a structure'20036,593,616'Buried bit line memory circuitry'20036,552,408'Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes'20036,548,390'SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY'20036,514,842'Low resistance gate flash memory'20036,489,226'SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY'20026,461,967'Material removal method for forming a structure'20026,455,394'Method for trench isolation by selective deposition of low temperature oxide films'20026,455,407'Methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry'20026,436,818'Semiconductor structure having a doped conductive layer'20026,436,831'Methods of forming insulative plugs and oxide plug forming methods'20026,429,496'Ion-assisted oxidation methods and the resulting structures'20026,423,620'SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY DRAM CIRCUITRY'20026,399,504'Methods and etchants for etching oxides of silicon with low selectivity'20026,395,620'Method for forming a planar surface over low density field areas on a semiconductor wafer'20026,391,793'Compositions for etching silicon with high selectivity to oxides and methods of using same'20026,391,756'Semiconductor processing methods of forming contact openings'20026,368,962'Semiconductor processing method of forming a conductive line, and buried bit line memory circuitry'20026,362,086'Forming a conductive structure in a semiconductor device'20026,355,580'Ion-assisted oxidation methods and the resulting structures'20026,340,627'Method of making a doped silicon diffusion barrier region'20026,337,274'Methods of forming buried bit line memory circuitry'20026,335,270'Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry'20026,333,243'Method for growing field oxide to minimize birds\' beak length'20016,322,634'Shallow trench isolation structure without corner exposure'20016,309,975'Methods of making implanted structures'20016,291,868'Forming a conductive structure in a semiconductor device'20016,288,419'Low resistance gate flash memory'20016,261,964'Material removal method for forming a structure'20016,259,127'Integrated circuit container having partially rugged surface'20016,210,489'Methods and etchants for etching oxides of silicon with low selectivity'20016,204,173'Multiple implantation and grain growth method'20016,198,144'Passivation of sidewalls of a word line stack'20016,191,037'Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes'20016,130,137'Method of forming a resistor and integrated circuitry having a resistor construction'20006,100,592'Integrated circuitry and method of forming a contact landing pad'20006,100,156'Method for forming a contact intermediate two adjacent electrical components'20006,100,189'Second implant for agglomeration control'20006,093,652'Methods of forming insulative plugs, and oxide plug forming methods'20006,093,953'Isolation regions and methods of forming isolation regions'20006,087,254'Technique for elimination of pitting on silicon substrate during gate stack etch'20006,080,645'Method of making a doped silicon diffusion barrier region'20006,075,274'Semiconductor devices having gate stack with improved sidewall integrity'20006,069,059'Well-drive anneal technique using preplacement of nitride films for enhanced field isolation'20006,067,680'Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening'20006,066,544'Isolation regions and methods of forming isolation regions'20006,057,200'Method of making a field effect transistor having an elevated source and an elevated drain'20006,054,744'Metal silicide film stress control by grain boundary stuffing'20006,027,984'Method for growing oxide'20006,015,997'Semiconductor structure having a doped conductive layer'20006,004,879'Method for fabricating a structure on a cobalt silicide oxide metalization semiconductor substrate'19995,998,290'Method to protect gate stack material during source/drain reoxidation'19995,998,844'Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon'19995,940,712'Method of forming a resistor and integrated circuitry having a resistor construction'19995,930,641'Method for forming an integrated circuit container having partially rugged surface'19995,925,918'Gate stack with improved sidewall integrity'19995,923,078'Method of forming a resistor and integrated circuitry having a resistor construction'19995,874,351'Sputtered metal silicide film stress control by grain boundary stuffing'19995,856,698'Second implanted matrix for agglomeration control and thermal stability'19995,854,127'Method of forming a contact landing pad'19985,834,358'Isolation regions and methods of forming isolation regions'19985,831,334'Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon'19985,821,150'Method of forming a resistor and integrated circuitry having a resistor construction'19985,801,413'Container-shaped bottom electrode for integrated circuit capacitor with partially rugged surface'19985,780,920'Method of forming a resistor and integrated circuitry having a resistor construction'19985,776,815'Method for forming a contact intermediate two adjacent electrical components'19985,763,923'Compound PVD target material for semiconductor metallization'19985,763,932'Isolation regions and methods of forming isolation regions'19985,759,905'Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening'19985,741,738'Method of making corner protected shallow trench field effect transistor'19985,739,064'Second implanted matrix for agglomeration control and thermal stability'19985,739,066'Semiconductor processing methods of forming a conductive gate and line'19985,736,455'Method for passivating the sidewalls of a tungsten word line'19985,716,535'Methods and etchants for etching oxides of silicon with low selectivity'19985,712,186'Method for growing field oxide to minimize birds\' beak length'19985,686,345'Trench mask for forming deep trenches in a semiconductor substrate, and method of using same'19975,677,573'Field effect transistor'19975,668,037'Method of forming a resistor and integrated circuitry having a resistor construction'19975,637,518'Method of making a field effect transistor having an elevated source and an elevated drain'19975,618,751'Method of making single-step trenches using resist fill and recess'19975,521,422'Corner protected shallow trench isolation device'19965,434,109'Oxidation of silicon nitride in semiconductor devices'19955,412,246'Low temperature plasma oxidation process'19955,330,935'Low temperature plasma oxidation process'19944,725,560'Silicon oxynitride storage node dielectric'19884,631,219'Growth of bird\'s beak free semi-rox'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–1998Patents assigned to IBM (9)· patent assignee history
1986–1988Based in Essex Junction, VT, US· patent location history
1994–1995Based in Hopewell Junction, NY, US· patent location history
1996–2014Based in Boise, ID, US· patent location history
1997–2014Patents assigned to MICRON TECHNOLOGY INC (104)· patent assignee history
1999Patents assigned to MICRON TECNOLOGY INC (1)· patent assignee history
2012–2014Patents assigned to PAN PAI-HUNG (3)· patent assignee history
2013Patents assigned to LI LI (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC1041997–2014
IBM91986–1998
PAN PAI-HUNGself32012–2014
LI LI12013
MICRON TECNOLOGY INC11999
Locations
LocationPatentsSpan
Boise, ID, US1101996–2014
Hopewell Junction, New York, US31994–1995
Essex Junction, VT, US21986–1988