USPatentGranted
B1

Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof

Granted 13 Jan 2004 · 10 office actions

Assignee: Micron Technology, Inc.

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Inventors: Pai-Hung Pan, Ravi Iyer, Louie Liu · Examiner: Benjamin L. Utech

Application
9614113
filed 12 Jul 2000
Publication
Not published
not published
Patent· this page
US 6,677,241
granted 13 Jan 2004

Life of the patent

23 dated events
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Abstract

A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Classifications

5 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L2/1302
USPC · US Patent Classification
438/706438/720438/724438/725

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File wrapper

⤢ drag to zoomJul 2000Jan 2001Jul 2001Jan 2002Jul 2002Jan 2003Jul 2003Jan 2004USPTOApplicantRestriction requirementResponse after non-finalResponse after finalNon-final rejectionResponse after non-finalResponse after finalRequest for continued examination
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Pendency
3.5 y
1,280 days filing → grant
Office actions
5
after a restriction
Responses
6
2 RCE
Examiner
Benjamin L. Utech
art unit —
Citations: 18 back · 0 forward

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