Inventor
Martin Gutsche
Inventor
Dorfen, DE
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices27%
H10DInorganic electric semiconductor devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
C23CCoating metallic material5%
H10NElectric solid-state devices not otherwise provided for4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
B82YSpecific uses or applications of nanostructures4%
G11CStatic stores2%
C23FNon-mechanical removal of metallic material from surface1%
PatentTitleYear
9,177,995'Vertical interconnect structure, memory device and associated production method'20158,420,526'Vertical interconnect structure, memory device and associated production method'20138,298,932'Vertical interconnect structure, memory device and associated production method'20128,084,190'Process for producing sublithographic structures'20118,049,264'Method for producing a dielectric material on a semiconductor device and semiconductor device'20117,998,858'Vertical interconnect structure, memory device and associated production method'20117,605,090'Process for producing sublithographic structures'20097,456,461'Stacked capacitor array and fabrication method for a stacked capacitor array'20087,420,199'Resistivity changing memory cell having nanowire electrode'20087,361,549'Method for fabricating memory cells for a memory device'20087,348,619'Ferroelectric memory arrangement'20087,316,951'Fabrication method for a trench capacitor having an insulation collar'20087,317,201'Method of producing a microelectronic electrode structure, and microelectronic electrode structure'20087,312,115'Fabrication method for a semiconductor structure having integrated capacitors'20077,303,970'Method of fabricating dielectric mixed layers and capacitive element and use thereof'20077,186,607'Charge-trapping memory device and method for production'20077,176,514'Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material'20077,170,125'Capacitor with electrodes made of ruthenium and method for patterning layers made of ruthenium or ruthenium'20077,157,371'Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices'20077,138,677'Capacitor arrangement with capacitors arranged one in the other'20067,122,423'Method for fabricating a memory cell'20067,119,395'Memory cell with nanocrystals or nanodots'20067,112,487'Method for fabricating a stacked capacitor array having a regular arrangement of a plurality of stacked capacitors'20067,087,485'Method of fabricating an oxide collar for a trench capacitor'20067,084,454'Nonvolatile integrated semiconductor memory'20067,081,383'Method for fabricating memory cells and memory cell array'20067,074,689'Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell'20066,977,405'Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it'20056,953,722'Method for patterning ceramic layers'20056,949,269'Method for producing vertical patterned layers made of silicon dioxide'20056,916,704'Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor'20056,852,640'Method for fabricating a hard mask'20056,849,153'Removal of post-rie polymer on A1/CU metal line'20056,835,417'Method and device for depositing thin layers via ALD/CVD processes in combination with rapid thermal processes'20046,774,005'Method for fabricating a metal carbide layer and method for fabricating a trench capacitor containing a metal carbide'20046,693,016'Method of fabricating a trench-structure capacitor device'20046,653,185'Method of providing trench walls by using two-step etching processes'20036,579,758'Method and installation for fabricating one-sided buried straps'20036,559,005'Method for fabricating capacitor electrodes'20036,548,414'Method of plasma etching thin films of difficult to dry etch materials'20036,455,369'Method for fabricating a trench capacitor'20026,437,387'Memory cell with a stacked capacitor'20026,420,099'Tungsten hard mask for dry etching aluminum-containing layers'20026,207,584'High dielectric constant material deposition to achieve high capacitance'20016,207,524'Memory cell with a stacked capacitor'20016,177,353'Metallization etching techniques for reducing post-etch corrosion of metal lines'20016,136,660'Stacked capacitator memory cell and method of fabrication'20006,033,977'Dual damascene structure'20005,980,770'Removal of post-RIE polymer on Al/Cu metal line'19995,935,873'Deposition of carbon into nitride layer for improved selectivity of oxide to nitride etchrate for self aligned contact etching'19995,854,126'Method for forming metallization in semiconductor devices with a self-planarizing material'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2005Patents assigned to SIEMENS AG (8)· patent assignee history
1998–2000Based in Poughkeepsie, NY, US· patent location history
1999–2005Patents assigned to IBM (5)· patent assignee history
2000–2015Based in Dorfen, DE· patent location history
2001–2005Based in Neufahrn, DE· patent location history
2001Based in Dammerlberg, DE· patent location history
2002–2015Patents assigned to INFINEON TECHNOLOGIES AG (39)· patent assignee history
2003Based in Dorpen, DE· patent location history
2011–2015Patents assigned to GUTSCHE MARTIN (3)· patent assignee history
2011–2015Patents assigned to SEIDL HARALD (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 39 | 2002–2015 |
| SIEMENS AG | 8 | 1998–2005 |
| IBM | 5 | 1999–2005 |
| GUTSCHE MARTINself | 3 | 2011–2015 |
| SEIDL HARALD | 3 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dorfen, DE | 42 | 2000–2015 |
| Poughkeepsie, New York, US | 4 | 1998–2000 |
| Neufahrn, DE | 3 | 2001–2005 |
| Dorpen, DE | 1 | 2003 |
| Dammerlberg, DE | 1 | 2001 |