Inventor

Laurence H. Cooke

Inventor

Los Gatos, CA, US

Overview

90→

Patents

1979–2021

Patent span

Physics

Primary field (CPC G)

Patents· 90 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing21%

G01RMeasuring electric variables14%

G11CStatic stores9%

H03KPulse technique9%

H01LSemiconductor devices6%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%

Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%

B82YSpecific uses or applications of nanostructures2%

G02BOptical elements, systems or apparatus2%

G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein2%

PatentTitleYear

11,114,633Solar antenna array fabrication2021 10,622,503Solar antenna array fabrication2020 10,580,920Solar antenna array fabrication2020 10,437,371Low power semi-reflective display2019 10,170,177Manufacture of a tunnel diode memory2019 10,095,636Secure computing2018 10,072,642Uses of hydrocarbon nanorings2018 10,042,453Low-power semi-reflective display2018 9,960,480Solar antenna array and its fabrication2018 9,917,217'Solar antenna array and its fabrication and uses'2018 9,917,225'Black body infrared antenna array'2018 9,846,656Secure computing2017 9,823,689'Variable clocked serial array processor'2017 9,502,449'Low-power semi-reflective display'2016 9,407,248'Tunable clock system'2016 9,391,161'Manufacture of a tunnel diode memory'2016 9,329,621'Variable clocked serial array processor'2016 9,280,490'Secure computing'2016 9,219,118'Use of hydrocarbon nanorings for data storage'2015 9,164,559'Low power semi-reflective display'2015 9,130,597'Non-volatile memory error correction'2015 9,129,042'Nearest neighbor serial content addressable memory'2015 9,124,256'Tunable clock system'2015 9,007,798'Nearest neighbor serial content addressable memory'2015 9,000,660'Uses of hydrocarbon nanorings'2015 8,996,938'On-chip service processor'2015 8,958,265'Nearest neighbor serial content addressable memory'2015 8,928,387'Tunable clock distribution system'2015 8,907,707'Aligning multiple chip input signals using digital phase lock loops'2014 8,743,578'Use of hydrocarbon nanorings for data storage'2014 8,692,596'Aligning multiple chip input signals using digital phase lock loops'2014 8,656,143'Variable clocked heterogeneous serial array processor'2014 RE044764'Serially decoded digital device testing'2014 8,593,191'Aligning multiple chip input signals using digital phase lock loops'2013 8,339,824'Nearest neighbor serial content addressable memory'2012 8,239,716'On-chip service processor'2012 8,166,278'Hashing and serial decoding techniques'2012 8,085,567'Iterative serial content addressable memory'2011 7,890,899'Variable clocked scan test improvements'2011 7,836,371'On-chip service processor'2010 7,818,538'Hashing and serial decoding techniques'2010 7,797,595'Serially decoded digital device testing'2010 7,752,515'Accelerated scan circuitry and method for reducing scan test data volume and execution time'2010 RE041187'Variable clocked scan test circuitry and method'2010 7,649,759'Serial content addressable memory'2010 7,620,865'Scan string segmentation for digital test compression'2009 7,594,205'Interface configurable for use with target/initiator signals'2009 7,463,062'Structured integrated circuit device'2008 7,439,773'Integrated circuit communication techniques'2008 7,421,563'Hashing and serial decoding techniques'2008 7,412,636'Scan string segmentation for digital test compression'2008 7,369,422'Serial content addressable memory'2008 7,353,470'Variable clocked scan test improvements'2008 7,249,340'Adaptable circuit blocks for use in multi-block chip design'2007 7,234,092'Variable clocked scan test circuitry and method'2007 7,200,784'Accelerated scan circuitry and method for reducing scan test data volume and execution time'2007 7,197,681'Accelerated scan circuitry and method for reducing scan test data volume and execution time'2007 7,188,286'Accelerated scan circuitry and method for reducing scan test data volume and execution time'2007 7,181,705'Hierarchical test circuit structure for chips with multiple circuit blocks'2007 7,105,871'Semiconductor device'2006 7,100,124'Interface configurable for use with target/initiator signals'2006 7,080,301'On-chip service processor'2006 6,968,514'Block based design methodology with programmable components'2005 6,964,001'On-chip service processor'2005 6,901,562'Adaptable circuit blocks for use in multi-block chip design'2005 6,886,121'Hierarchical test circuit structure for chips with multiple circuit blocks'2005 6,816,996'Hierarchical test circuit structure for chips with multiple circuit blocks'2004 6,708,325'Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic'2004 6,701,474'System and method for testing integrated circuits'2004 6,687,865'On-chip service processor for test and debug of integrated circuits'2004 6,651,237'System and method for H-Tree clocking layout'2003 6,631,504'Hierarchical test circuit structure for chips with multiple circuit blocks'2003 6,389,579'Reconfigurable logic for table lookup'2002 6,282,627'Integrated processor and programmable data path chip for reconfigurable computing'2001 5,970,254'Integrated processor and programmable data path chip for reconfigurable computing'1999 5,966,534'Method for compiling high level programming languages into an integrated processor with reconfigurable logic'1999 5,887,002'Preprogramming testing in a field programmable gate array'1999 5,777,887'FPGA redundancy'1998 5,671,234'Programmable input/output buffer circuit with test capability'1997 5,652,527'Input-output circuit for increasing immunity to voltage spikes'1997 5,623,501'Preprogramming testing in a field programmable gate array'1997 5,534,798'Multiplexer with level shift capabilities'1996 5,394,103'Field programmable gate array'1995 5,347,519'Preprogramming testing in a field programmable gate array'1994 5,313,119'Field programmable gate array'1994 5,221,865'Programmable input/output buffer circuit with test capability'1993 5,130,568'Scannable latch system and method'1992 4,540,903'Scannable asynchronous/synchronous CMOS latch'1985 4,147,937'Electron beam exposure system method and apparatus'1979 4,132,898'Overlapping boundary electron exposure system method and apparatus'1979

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1979Based in Cupertino, CA, US· patent location history

1985Based in Santa Clara, CA, US· patent location history

1992–1999Based in San Jose, CA, US· patent location history

1993–1999Patents assigned to CROSSPOINT SOLUTIONS INC (9)· patent assignee history

1999–2021Based in Los Gatos, CA, US· patent location history

2003–2009Patents assigned to CADENCE DESIGN SYSTEMS INC (10)· patent assignee history

2004–2010Patents assigned to ON CHIP TECHNOLOGIES INC (9)· patent assignee history

2009–2019Patents assigned to COOKE LAURENCE H (37)· patent assignee history

2009–2014Based in Aptos, CA, US· patent location history

2015–2021Patents assigned to NOVASOLIX INC (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
COOKE LAURENCE Hself	37	2009–2019
CADENCE DESIGN SYSTEMS INC	10	2003–2009
NOVASOLIX INC	10	2015–2021
CROSSPOINT SOLUTIONS INC	9	1993–1999
ON CHIP TECHNOLOGIES INC	9	2004–2010

Locations

Location	Patents	Span
Los Gatos, California, US	69	1999–2021
San Jose, California, US	11	1992–1999
Aptos, California, US	7	2009–2014
Cupertino, California, US	2	1979
Santa Clara, California, US	1	1985