Inventor
Shang-Yun Hou
Inventor
Jubei, TW
Overview
Patents· 161 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H01LSemiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10DInorganic electric semiconductor devices5%
G01RMeasuring electric variables3%
H10BElectronic memory devices2%
H05KPrinted circuits2%
G02BOptical elements, systems or apparatus1%
B23KSoldering or unsoldering1%
C23CCoating metallic material1%
PatentTitleYear
11,121,118Integrated circuit stacking approach202111,101,260Method of forming a dummy die of an integrated circuit having an embedded annular structure202111,101,236Semiconductor package and method of forming the same202111,101,140Semiconductor device and method of manufacture202111,081,372Package system for integrated circuits202111,069,657Chip package having die structures of different heights and method of forming same202111,069,5393D packages and methods for forming the same202110,985,137Stacked integrated circuit structure and method of forming202110,985,125Chip package structure202110,978,346Conductive vias in semiconductor packages and methods of forming same202110,964,667Stacked integrated circuit structure and method of forming202110,948,668Package structure for optical fiber and method for forming the same202110,886,147Package structure and method for forming the same202110,872,871Chip package structure with dummy bump and method for forming the same202010,867,954Interconnect chips202010,866,373Optical transceiver and manufacturing method thereof202010,866,374Optical bench on substrate and method of making the same202010,854,5673D packages and methods for forming the same202010,847,485Chip package structure and method for forming the same202010,790,254Chip package structure202010,770,365Package structures and methods of forming the same202010,746,923Photonic semiconductor device and method202010,748,870Tri-layer COWOS structure202010,734,295Interposer test structures and methods202010,720,401Interconnect chips202010,665,4743D packages and methods for forming the same202010,663,512Testing of semiconductor chips with microbumps202010,656,351Package structure for optical fiber and method for forming the same202010,535,633Chip package having die structures of different heights and method of forming same202010,529,6793D packages and methods for forming the same202010,515,888Semiconductor device and method for manufacturing the same201910,515,829Package system for integrated circuits201910,515,906Forming large chips through stitching201910,515,869Semiconductor package structure having a multi-thermal interface material structure201910,510,722Semiconductor device and method for manufacturing the same201910,510,603Conductive vias in semiconductor packages and methods of forming same2019RE047709Forming grounded through-silicon vias in a semiconductor substrate201910,446,5203D semiconductor package interposer with die cavity201910,319,699Chip package having die structures of different heights201910,304,800Packaging with substrates connected by conductive bumps201910,269,5843D packages and methods for forming the same201910,262,939Configurable routing for packaging applications201910,175,294Testing of semiconductor chips with microbumps201910,170,457COWOS structures and method of forming the same201910,163,853Formation method of chip package201810,163,856Stacked integrated circuit structure and method of forming201810,163,851Tri-layer CoWoS structure201810,153,205Package with metal-insulator-metal capacitor and method of manufacturing the same201810,153,338Method of manufacturing a capacitor201810,153,222Package structures and methods of forming the same201810,090,213Interposer test structures and methods201810,056,347Bump structure for yield improvement20189,984,981Packages with interposers and methods for forming the same20189,978,637Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs)20189,953,948Pillar design for conductive bump20189,859,235'Underbump metallization structure'20189,818,720'Structure and formation method for chip package'20179,806,038'Reinforcement structure and method for controlling warpage of chip mounted on substrate'20179,806,058'Chip package having die structures of different heights and method of forming same'20179,786,567'Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages'20179,780,072'3D semiconductor package interposer with die cavity'20179,760,670'Semiconductor device design methods and conductive bump pattern enhancement methods'20179,741,638'Thermal structure for integrated circuit package'20179,741,669'Forming large chips through stitching'20179,691,840'Cylindrical embedded capacitors'20179,660,016'Method of manufacturing a capacitor'20179,640,490'Through silicon via keep out zone formation method and system'20179,633,869'Packages with interposers and methods for forming the same'20179,627,223'Methods and apparatus of packaging with interposers'20179,627,365'Tri-layer CoWoS structure'20179,618,572'Testing of semiconductor chips with microbumps'20179,618,712'Optical bench on substrate and method of making the same'20179,601,443'Test structure for seal ring quality monitor'20179,589,857'Interposer test structures and methods'20179,581,638'Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages'20179,570,324'Method of manufacturing package system'20179,570,366'Passivation layer for packaged chip'20179,553,053'Bump structure for yield improvement'20179,530,730'Configurable routing for packaging applications'20169,508,666'Packaging structures and methods with a metal pillar'20169,502,271'Warpage control for flexible substrates'20169,502,380'Three dimensional integrated circuits stacking approach'20169,496,235'Pillar design for conductive bump'20169,462,692'Test structure and method of testing electrical characteristics of through vias'20169,412,678'Structure and method for 3D IC package'20169,385,091'Reinforcement structure and method for controlling warpage of chip mounted on substrate'20169,385,095'3D semiconductor package interposer with die cavity'20169,372,951'Semiconductor device design methods and conductive bump pattern enhancement methods'20169,372,206'Testing of semiconductor chips with microbumps'20169,337,123'Thermal structure for integrated circuit package'20169,305,808'Methods and apparatus of packaging with interposers'20169,299,649'3D packages and methods for forming the same'20169,263,511'Package with metal-insulator-metal capacitor and method of manufacturing the same'20169,209,156'Three dimensional integrated circuits stacking approach'20159,159,673'Forming interconnect structures using pre-ink-printed sheets'20159,128,123'Interposer test structures and methods'20159,116,203'Testing of semiconductor chips with microbumps'20159,064,705'Methods and apparatus of packaging with interposers'20159,054,166'Through silicon via keep out zone formation method and system'20159,048,233'Package systems having interposers'20159,048,231'3D packages and methods for forming the same'20159,040,381'Packages with passive devices and methods of forming the same'20159,034,695'Integrated thermal solutions for packaging integrated circuits'20158,993,432'Test structure and method of testing electrical characteristics of through vias'20158,993,355'Test line placement to improve die sawing quality'20158,993,380'Structure and method for 3D IC package'20158,937,389'Semiconductor devices comprising GSG interconnect structures'20158,901,735'Connector design for packaging integrated circuits'20148,896,089'Interposers for semiconductor devices and methods of manufacture thereof'20148,878,338'Capacitor for interposers and methods of manufacture thereof'20148,878,182'Probe pad design for 3DIC package yield analysis'20148,872,345'Forming grounded through-silicon vias in a semiconductor substrate'20148,865,521'3D semiconductor package interposer with die cavity'20148,860,208'Heat spreader structures in scribe lines'20148,836,094'Package device including an opening in a flexible substrate and methods of forming the same'20148,816,498'Pillar design for conductive bump'20148,810,006'Interposer system and method'20148,802,504'3D packages and methods for forming the same'20148,797,057'Testing of semiconductor chips with microbumps'20148,765,549'Capacitor for interposers and methods of manufacture thereof'20148,759,150'Approach for bonding dies onto interposers'20148,753,971'Dummy metal design for packaging structures'20148,716,867'Forming interconnect structures using pre-ink-printed sheets'20148,693,163'Cylindrical embedded capacitors'20148,680,647'Packages with passive devices and methods of forming the same'20148,664,760'Connector design for packaging integrated circuits'20148,643,147'Seal ring structure with improved cracking protection and reduced problems'20148,610,285'3D IC packaging structures and methods with a metal pillar'20138,604,619'Through silicon via keep out zone formation along different crystal orientations'20138,575,717'Integrated circuit device and method of manufacturing the same'20138,558,229'Passivation layer for packaged chip'20138,519,537'3D semiconductor package interposer with die cavity'20138,519,512'Test line placement to improve die sawing quality'20138,368,180'Scribe line metal structure'20138,334,582'Protective seal ring for preventing die-saw induced stress'20128,319,349'Approach for bonding dies onto interposers'20128,283,781'Semiconductor device having pad structure with stress buffer layer'20128,227,917'Bond pad design for fine pitch wire bonding'20128,193,639'Dummy metal design for packaging structures'20128,125,052'Seal ring structure with improved cracking protection'20128,105,875'Approach for bonding dies onto interposers'20128,072,076'Bond pad structures and integrated circuit chip having the same'20118,030,776'Integrated circuit with protective structure'20117,952,167'Scribe line layout design'20117,906,836'Heat spreader structures in scribe lines'20117,888,236'Semiconductor device and fabrication methods thereof'20117,811,866'Single passivation layer scheme for forming a fuse'20107,776,627'Flexible structures for interconnect reliability test'20107,714,443'Pad structure design with reduced density'20107,651,893'Metal electrical fuse structure'20107,602,065'Seal ring in semiconductor device'20097,449,785'Solder bump on a semiconductor substrate'20087,446,398'Bump pattern design for flip chip semiconductor package'20087,397,106'Laser fuse with efficient heat dissipation'20087,364,998'Method for forming high reliability bump structure'20087,205,588'Metal fuse for semiconductor devices'20076,854,100'Methodology to characterize metal sheet resistance of copper damascene process'20056,777,318'Aluminum/copper clad interconnect layer for VLSI applications'20046,753,210'Metal fuse for semiconductor devices'20045,981,386'Method for manufacturing interconnection plug'19995,948,216'Method for making thin film tantalum oxide layers with enhanced dielectric properties and capacitors employing such layers'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2020Based in Hsinchu, TW· patent location history
1999Based in Summit, NJ, US· patent location history
2004–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (73)· patent assignee history
2008–2021Based in Jubei, TW· patent location history
2011–2018Patents assigned to HOU SHANG-YUN (39)· patent assignee history
2012–2018Patents assigned to JENG SHIN-PUU (35)· patent assignee history
2012–2018Patents assigned to YU CHEN-HUA (20)· patent assignee history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (88)· patent assignee history
2017–2018Based in Zhubei City, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 88 | 2015–2021 |
| TAIWAN SEMICONDUCTOR MFG | 73 | 2004–2016 |
| HOU SHANG-YUNself | 39 | 2011–2018 |
| JENG SHIN-PUU | 35 | 2012–2018 |
| YU CHEN-HUA | 20 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jubei, TW | 134 | 2008–2021 |
| Hsinchu, TW | 23 | 1999–2020 |
| Zhubei City, TW | 3 | 2017–2018 |
| Summit, New Jersey, US | 1 | 1999 |