Inventor

Marko Radosavljevic

Inventor

Beaverton, OR, US

Overview

2005–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 270 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices24%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

B82YSpecific uses or applications of nanostructures8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

H03HImpedance networks, e.g. resonant circuits1%

G11CStatic stores1%

H10NElectric solid-state devices not otherwise provided for1%

H04BTransmission1%

PatentTitleYear

11,133,410Field-effect transistors and methods of manufacturing the same2021 11,114,556Gate stack design for GaN e-mode transistor performance2021 11,107,764Group III-V semiconductor fuses and their methods of fabrication2021 11,101,380Group III-nitride integrated front-end circuit2021 11,101,270Techniques and mechanisms for operation of stacked transistors2021 11,081,483CMOS circuit with a group III-nitride transistor and method of providing same2021 11,056,532Techniques for monolithic co-integration of polycrystalline thin-film bulk acoustic resonator devices and monocrystalline III-N semiconductor transistor devices2021 11,056,449Guard ring structures and their methods of fabrication2021 11,043,627Techniques for monolithic co-integration of thin-film bulk acoustic resonator devices and III-N semiconductor transistor devices2021 11,031,305Laterally adjacent and diverse group III-N transistors2021 11,031,387PN diodes and connected group III-N devices and their methods of fabrication2021 11,005,447Microelectronic devices having vertical piezoelectric membranes for integrated RF filters2021 10,998,260Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances2021 10,991,817Group III-N transistors including source to channel heterostructure design2021 10,979,012Single-flipped resonator devices with 2DEG bottom electrode2021 10,950,733Deep gate-all-around semiconductor device having germanium or group III-V active layer2021 10,943,836Gallium nitride NMOS on Si (111) co-integrated with a silicon PMOS2021 10,937,907Method for fabricating transistor with thinned channel2021 10,930,791Systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in source and drain for low access and contact resistance of thin film transistors2021 10,930,500Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices2021 10,923,584Graded channels for high frequency III-N transistors2021 10,879,346Capacitor including multilayer dielectric stack2020 10,879,134Techniques for monolithic co-integration of silicon and III-N semiconductor transistors2020 10,861,942Tunable capacitors including III-N multi-2DEG and 3DEG structures for tunable RF filters2020 10,850,977Group III-N MEMS structures on a group IV substrate2020 10,848,127Film bulk acoustic resonator (FBAR) RF filter having epitaxial layers2020 10,847,656Fabrication of non-planar IGZO devices for improved electrostatics2020 10,847,624Methods and apparatus to form GaN-based transistors during back-end-of-the-line processing2020 10,840,341Semiconductor devices, radio frequency devices and methods for forming semiconductor devices2020 10,811,526Stacked group III-nitride transistors for an RF switch and methods of fabrication2020 10,811,501InN tunnel junction contacts for P-channel GaN2020 10,804,386Gate stack design for GaN e-mode transistor performance2020 10,804,214Group III-N material conductive shield for high frequency metal interconnects2020 10,804,359Geometric manipulation of 2DEG region in source/drain extension of GaN transistor2020 10,804,879Film bulk acoustic resonator (FBAR) devices for high frequency RF filters2020 10,790,332Techniques for integrating three-dimensional islands for radio frequency (RF) circuits2020 10,784,170CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture2020 10,784,360Transistor gate trench engineering to decrease capacitance and resistance2020 10,777,672Gallium nitride transistors for high-voltage radio frequency switches2020 10,777,671Layered spacer formation for ultrashort channel lengths and staggered field plates2020 10,770,575Vertical group III-N devices and their methods of fabrication2020 10,770,551P-I-N diode and connected group III-N device and their methods of fabrication2020 10,763,248Multi-layer silicon/gallium nitride semiconductor2020 10,763,350Transistor connected diodes and connected III-N devices and their methods of fabrication2020 10,756,183N-channel gallium nitride transistors2020 10,727,339Selectively regrown top contact for vertical semiconductor devices2020 10,727,138Integration of single crystalline transistors in back end of line (BEOL)2020 10,727,2413D NAND structures including group III-N material channels2020 10,720,505Ferroelectric-based field-effect transistor with threshold voltage switching for enhanced on-state and off-state performance2020 10,707,136Gallium nitride NMOS on Si (111) co-integrated with a silicon PMOS2020 10,700,665Film bulk acoustic resonator (FBAR) devices for high frequency RF filters2020 10,693,008Cladding layer epitaxy via template engineering for heterogeneous integration on silicon2020 10,692,839GaN devices on engineered silicon substrates2020 10,673,405Film bulk acoustic resonator (FBAR) devices with 2DEG bottom electrode2020 10,672,884Schottky diodes on semipolar planes of group III-N material structures2020 10,665,707Techniques for co-integrating transition metal dichalcogenide (TMDC)-based and III-N semiconductor-based transistor devices2020 10,665,708Semiconductor devices with raised doped crystalline structures2020 10,665,577Co-integrated III-N voltage regulator and RF power amplifier for envelope tracking systems2020 10,658,502Vertical III-N transistors with lateral overgrowth over a protruding III-N semiconductor structure2020 10,658,475Transistors with vertically opposed source and drain metal interconnect layers2020 10,658,471Transition metal dichalcogenides (TMDCS) over III-nitride heteroepitaxial layers2020 10,644,140Integrated circuit die having back-end-of-line transistors2020 10,622,448Transistors including retracted raised source/drain to reduce parasitic capacitances2020 10,600,787Silicon PMOS with gallium nitride NMOS for voltage regulation2020 10,586,866Stressors for compressively strained GaN p-channel2020 10,580,895Wide band gap transistors on non-native semiconductor substrates2020 10,573,647CMOS circuits using n-channel and p-channel gallium nitride transistors2020 10,573,717Selective epitaxially grown III-V materials based devices2020 10,574,187Envelope-tracking control techniques for highly-efficient RF power amplifiers2020 10,553,689Multiple stacked field-plated GaN transistor and interlayer dielectrics to improve breakdown voltage and reduce parasitic capacitances2020 10,546,927Self-aligned transistor structures enabling ultra-short channel lengths2020 10,541,305Group III-N nanowire transistors2020 10,535,777Nanoribbon structures with recessed source-drain epitaxy2020 10,497,785Gallium nitride voltage regulator2019 10,475,888Integration of III-V devices on Si wafers2019 10,453,679Methods and devices integrating III-N transistor circuitry with Si transistor circuitry2019 10,431,717Light-emitting diode (LED) and micro LED substrates and methods for making the same2019 10,411,122Semiconductor device having group III-V material active region and graded gate dielectric2019 10,411,067Integrated RF frontend structures2019 10,388,777Heteroepitaxial structures with high temperature stable substrate interface material2019 10,367,093Method for fabricating transistor with thinned channel2019 10,347,834Wafer-scale integration of vacancy centers for spin qubits2019 10,347,544Co-planar p-channel and n-channel gallium nitride-based transistors on silicon and techniques for forming same2019 10,340,275Stackable thin film memory2019 10,332,998Transistors with heteroepitaxial III-N source/drain2019 10,325,774Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices2019 10,319,646CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture2019 10,290,614Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits2019 10,263,074High voltage field effect transistors2019 10,263,079Apparatus and methods for forming a modulation doped non-planar transistor2019 10,249,490Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy2019 10,243,069Gallium nitride transistor having a source/drain structure including a single-crystal portion abutting a 2D electron gas2019 10,236,369Techniques for forming non-planar germanium quantum well devices2019 10,229,991III-N epitaxial device structures on free standing silicon mesas2019 10,217,673Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith2019 10,211,327Semiconductor devices with raised doped crystalline structures2019 10,204,989Method of fabricating semiconductor structures on dissimilar substrates2019 10,186,581Group III-N nanowire transistors2019 10,181,518Selective epitaxially grown III-V materials based devices2019 10,177,249Techniques for forming contacts to quantum well transistors2019 10,170,612Epitaxial buffer layers for group III-N transistors on silicon substrates2019 10,096,709Aspect ratio trapping (ART) for fabricating vertical semiconductor devices2018 10,096,682III-N devices in Si trenches2018 10,096,683Group III-N transistor on nanoscale template structures2018 10,090,405Semiconductor device having group III-V material active region and graded gate dielectric2018 10,084,043High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin2018 10,084,058Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains2018 10,074,718Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack2018 10,056,456N-channel gallium nitride transistors2018 10,050,015Multi-device flexible electronics system on a chip (SOC) process integration2018 10,032,911Wide band gap transistor on non-native semiconductor substrate2018 10,026,845Deep gate-all-around semiconductor device having germanium or group III-V active layer2018 10,020,371Contact techniques and configurations for reducing parasitic resistance in nanowire transistors2018 9,991,172Forming arsenide-based complementary logic on a single substrate2018 9,972,686Germanium tin channel transistors2018 9,947,780High electron mobility transistor (HEMT) and method of fabrication2018 9,927,211'Cloaking system with waveguides'2018 9,923,087'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2018 9,922,826'Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith'2018 9,905,651'GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2018 9,899,505'Conductivity improvements for III-V semiconductor devices'2018 9,876,014Germanium-based quantum well devices2018 9,865,684'Nanoscale structure with epitaxial film having a recessed bottom portion'2018 9,853,107Selective epitaxially grown III-V materials based devices2017 9,847,432Forming III-V device structures on (111) planes of silicon fins2017 9,847,448Forming LED structures on silicon fins2017 9,818,847'Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface'2017 9,818,870'Transistor structure with variable clad/core dimension for stress and bandgap'2017 9,812,574'Techniques and configurations for stacking transistors of an integrated circuit device'2017 9,806,195'Method for fabricating transistor with thinned channel'2017 9,806,203'Nonplanar III-N transistors with compositionally graded semiconductor channels'2017 9,799,759'Techniques for forming non-planar germanium quantum well devices'2017 9,755,062'III-N material structure for gate-recessed transistors'2017 9,748,371'Transition metal dichalcogenide semiconductor assemblies'2017 9,748,338'Preventing isolation leakage in III-V devices'2017 9,716,149'Group III-N transistors on nanoscale template structures'2017 9,711,591'Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby'2017 9,704,981'Techniques for forming contacts to quantum well transistors'2017 9,698,222'Method of fabricating semiconductor structures on dissimilar substrates'2017 9,691,857'Group III-N nanowire transistors'2017 9,685,381'Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon'2017 9,685,508'High voltage field effect transistors'2017 9,673,045'Integration of III-V devices on Si wafers'2017 9,666,583'Methods of containing defects for non-silicon device engineering'2017 9,666,492'CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture'2017 9,666,708'III-N transistors with enhanced breakdown voltage'2017 9,660,067'III-N transistors with epitaxial layers providing steep subthreshold swing'2017 9,660,064'Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack'2017 9,660,085'Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof'2017 9,653,559'Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same'2017 9,653,548'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2017 9,640,537'Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy'2017 9,640,622'Selective epitaxially grown III-V materials based devices'2017 9,640,646'Semiconductor device having group III-V material active region and graded gate dielectric'2017 9,640,422'III-N devices in Si trenches'2017 9,640,671'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2017 9,634,007'Trench confined epitaxially grown device layer(s)'2017 9,590,069'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2017 9,583,574'Epitaxial buffer layers for group III-N transistors on silicon substrates'2017 9,570,614'Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2017 9,564,490'Apparatus and methods for forming a modulation doped non-planar transistor'2017 9,530,878'III-N material structure for gate-recessed transistors'2016 9,478,635'Germanium-based quantum well devices'2016 9,461,141'Contact techniques and configurations for reducing parasitic resistance in nanowire transistors'2016 9,461,160'Non-planar III-N transistor'2016 9,443,936'Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains'2016 9,397,188'Group III-N nanowire transistors'2016 9,391,181'Lattice mismatched hetero-epitaxial film'2016 9,373,693'Nonplanar III-N transistors with compositionally graded semiconductor channels'2016 9,362,369'Group III-N transistors on nanoscale template structures'2016 9,356,099'Techniques for forming contacts to quantum well transistors'2016 9,343,574'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2016 9,337,307'Method for fabricating transistor with thinned channel'2016 9,337,291'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2016 9,310,565'Cloaking system with waveguides'2016 9,263,557'Techniques for forming non-planar germanium quantum well devices'2016 9,257,346'Apparatus and methods for forming a modulation doped non-planar transistor'2016 9,258,114'Quantum key distribution (QSD) scheme using photonic integrated circuit (PIC)'2016 9,245,989'High voltage field effect transistors'2016 9,240,410'Group III-N nanowire transistors'2016 9,236,476'Techniques and configuration for stacking transistors of an integrated circuit device'2016 9,219,135'Germanium-based quantum well devices'2015 9,219,079'Group III-N transistor on nanoscale template structures'2015 9,209,290'III-N material structure for gate-recessed transistors'2015 9,153,671'Techniques for forming non-planar germanium quantum well devices'2015 9,136,343'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2015 9,123,567'CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture'2015 9,123,790'Contact techniques and configurations for reducing parasitic resistance in nanowire transistors'2015 9,112,028'Methods of containing defects for non-silicon device engineering'2015 9,105,344'Shut-off mechanism in an integrated circuit device'2015 9,099,490'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2015 9,054,190'Methods of containing defects for non-silicon device engineering'2015 9,029,835'Epitaxial film on nanoscale structure'2015 9,018,680'Non-planar semiconductor device having active region with multi-dielectric gate stack'2015 9,006,707'Forming arsenide-based complementary logic on a single substrate'2015 8,987,091'III-N material structure for gate-recessed transistors'2015 8,954,021'Group III-N transistors on nanoscale template structures'2015 8,936,976'Conductivity improvements for III-V semiconductor devices'2015 8,896,101'Nonplanar III-N transistors with compositionally graded semiconductor channels'2014 8,890,118'Tunnel field effect transistor'2014 8,890,264'Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface'2014 8,883,573'Isolation for nanowire devices'2014 8,872,225'Defect transferred and lattice mismatched epitaxial film'2014 8,872,160'Increasing carrier injection velocity for integrated circuit devices'2014 8,853,067'Method of isolating nanowires from a substrate'2014 8,846,480'Carrier mobility in surface-channel transistors, apparatus made therewith, and system containing same'2014 8,823,059'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2014 8,809,836'Techniques for forming contacts to quantum well transistors'2014 8,785,907'Epitaxial film growth on patterned substrate'2014 8,785,909'Non-planar semiconductor device having channel region with low band-gap cladding layer'2014 8,765,563'Trench confined epitaxially grown device layer(s)'2014 8,768,271'Group III-N transistors on nanoscale template structures'2014 8,748,269'Quantum-well-based semiconductor devices'2014 8,716,751'Methods of containing defects for non-silicon device engineering'2014 8,710,490'Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer'2014 8,633,470'Techniques and configurations to impart strain to integrated circuit devices'2014 8,633,471'Apparatus and methods for forming a modulation doped non-planar transistor'2014 8,592,803'Germanium-based quantum well devices'2013 8,575,596'Non-planar germanium quantum well devices'2013 8,536,621'Quantum-well-based semiconductor devices'2013 8,525,162'Method of isolating nanowires from a substrate'2013 8,501,508'Method of forming quantum well mosfet channels having uni-axial strains caused by metal source/drains'2013 8,440,998'Increasing carrier injection velocity for integrated circuit devices'2013 8,415,751'Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain'2013 8,384,128'Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same'2013 8,368,052'Techniques for forming contacts to quantum well transistors'2013 8,350,291'Modulation-doped multi-gate devices'2013 8,344,425'Multi-gate III-V quantum well structures'2013 8,344,418'Materials for interfacing high-K dielectric layers with III-V semiconductors'2013 8,324,661'Quantum well transistors with remote counter doping'2012 8,283,653'Non-planar germanium quantum well devices'2012 8,278,687'Semiconductor heterostructures to reduce short channel effects'2012 8,269,209'Isolation for nanowire devices'2012 8,258,498'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2012 8,258,543'Quantum-well-based semiconductor devices'2012 8,227,833'Dual layer gate dielectrics for non-silicon semiconductor devices'2012 8,211,771'Multiple-gate transistors and processes of making same'2012 8,193,523'Germanium-based quantum well devices'2012 8,168,508'Method of isolating nanowires from a substrate'2012 8,129,749'Double quantum well structures for transistors'2012 8,124,959'High hole mobility semiconductor device'2012 8,120,063'Modulation-doped multi-gate devices'2012 8,115,235'Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same'2012 8,106,440'Selective high-k dielectric film deposition for semiconductor device'2012 8,093,584'Self-aligned replacement metal gate process for QWFET devices'2012 8,063,447'Multiple-gate transistors and processes of making same'2011 8,017,933'Compositionally-graded quantum-well channels for semiconductor devices'2011 8,012,816'Double pass formation of a deep quantum well in enhancement mode III-V devices'2011 7,947,971'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2011 7,915,167'Fabrication of channel wraparound gate structure for field-effect transistor'2011 7,915,642'Apparatus and methods for forming a modulation doped non-planar transistor'2011 7,898,041'Block contact architectures for nanoscale channel transistors'2011 7,892,902'Group III-V devices with multiple spacer layers'2011 7,884,354'Germanium on insulator (GOI) semiconductor substrates'2011 7,879,675'Field effect transistor with metal source/drain regions'2011 7,868,318'Quantum well field-effect transistors with composite spacer structures, apparatus made therewith, and methods of using same'2011 7,863,710'Dislocation removal from a group III-V film grown on a semiconductor substrate'2011 7,858,481'Method for fabricating transistor with thinned channel'2010 7,759,142'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2010 7,670,894'Selective high-k dielectric film deposition for semiconductor device'2010 7,638,383'Faceted catalytic dots for directed nanotube growth'2009 7,638,169'Directing carbon nanotube growth'2009 7,608,883'Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric'2009 7,427,541'Carbon nanotube energy well (CNEW) field effect transistor'2008 7,390,947'Forming field effect transistors from conductors'2008 7,342,277'Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric'2008 7,279,375'Block contact architectures for nanoscale channel transistors'2007 7,170,120'Carbon nanotube energy well (CNEW) field effect transistor'2007 6,897,009'Fabrication of nanometer size gaps on an electrode'2005 6,843,850'Catalyst-free growth of single-wall carbon nanotubes'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005Based in Media, PA, US· patent location history

2005Based in Peasantville, NY, US· patent location history

2007–2021Patents assigned to INTEL CORP (266)· patent assignee history

2007–2021Based in Beaverton, OR, US· patent location history

2009–2021Based in Portland, OR, US· patent location history

2011–2019Patents assigned to RADOSAVLJEVIC MARKO (72)· patent assignee history

2011–2019Patents assigned to PILLARISETTY RAVI (56)· patent assignee history

2012–2019Patents assigned to DEWEY GILBERT (49)· patent assignee history

2012–2019Patents assigned to MUKHERJEE NILOY (39)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	266	2007–2021
RADOSAVLJEVIC MARKOself	72	2011–2019
PILLARISETTY RAVI	56	2011–2019
DEWEY GILBERT	49	2012–2019
MUKHERJEE NILOY	39	2012–2019

Locations

Location	Patents	Span
Beaverton, OR, US	171	2007–2021
Portland, OR, US	97	2009–2021
Media, Pennsylvania, US	1	2005
Peasantville, New York, US	1	2005