Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

Claims

23 · 4 independent · depth 2

23 granted claims

›1.independentA method for designing a static random access memory (SRAM) array with a substantially constant operational yield across a plurality of modes of opera…+7

›2.↳ 1The method of claim 1, wherein biasing each SRAM bit cell of the plurality of SRAM bit cells comprises biasing each SRAM bit cell of the plurality of …d2

›3.↳ 1The method of claim 1, wherein biasing each SRAM bit cell of the plurality of SRAM bit cells comprises biasing each SRAM bit cell of the plurality of …d2

›4.↳ 1The method of claim 1, wherein biasing each SRAM bit cell of the plurality of SRAM bit cells comprises biasing each SRAM bit cell of the plurality of …d2

›5.↳ 1The method of claim 1, wherein biasing each SRAM bit cell of the plurality of SRAM bit cells comprises over-driving a wordline corresponding to each S…d2

›6.↳ 1The method of claim 1, wherein biasing each SRAM bit cell of the plurality of SRAM bit cells comprises under-driving a wordline corresponding to each …d2

›7.↳ 1The method of claim 1, wherein biasing each SRAM bit cell of the plurality of SRAM bit cells comprises providing a bias voltage to a bitline correspon…d2

›8.↳ 1The method of claim 1, wherein biasing each SRAM bit cell of the plurality of SRAM bit cells comprises applying a bias voltage to a backgate correspon…d2

›9.independentA static random access memory (SRAM) array comprising:na biasing circuit;a plurality of SRAM bit cells, wherein:neach SRAM bit cell of the plurality o…+9

›10.↳ 9The SRAM array of claim 9, wherein each SRAM bit cell of the plurality of SRAM bit cells is further configured to be biased to operate in a higher per…d2

›11.↳ 9The SRAM array of claim 9, wherein each SRAM bit cell of the plurality of SRAM bit cells is further configured to be biased to operate in a nominal pe…d2

›12.↳ 9The SRAM array of claim 9, wherein each SRAM bit cell of the plurality of SRAM bit cells is further configured to be biased to operate in a lower powe…d2

›13.↳ 9The SRAM array of claim 9, wherein each SRAM bit cell of the plurality of SRAM bit cells is further configured to be biased by over-driving a wordline…d2

›14.↳ 9The SRAM array of claim 9, wherein each SRAM bit cell of the plurality of SRAM bit cells is further configured to be biased by under-driving a wordlin…d2

›15.↳ 9The SRAM array of claim 9, wherein each SRAM bit cell of the plurality of SRAM bit cells is further configured to be biased by providing a bias voltag…d2

›16.↳ 9The SRAM array of claim 9, wherein each SRAM bit cell of the plurality of SRAM bit cells is further configured to be biased by applying a bias voltage…d2

›17.↳ 9The SRAM array of claim 9 integrated into an integrated circuit (IC).d2

›18.↳ 9The SRAM array of claim 9 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a…d2

›19.independentA static random access memory (SRAM) array, comprising:na means for determining performance characteristics for each mode of operation of a plurality …+3

›23.independentA non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the proces…

Classifications

4 codes

IPC · International Patent Classification

Section G — Physics

G06F17/50
G11C11/00
G11C11/417
G11C11/412

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Connie Yoha

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