Inventor

Kyoji Yamashita

Inventor
Osaka, JP

Overview

46→
Patents
1991–2021
Patent span
Physics
Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices20%
G06TImage data processing or generation, in general16%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G01NInvestigating or analysing materials by determining their chemical or physical properties6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G06FElectric digital data processing5%
G06VImage or video recognition or understanding5%
G01RMeasuring electric variables4%
H10BElectronic memory devices4%
PatentTitleYear
11,110,599Robot, control device of robot, and method of teaching position of robot202111,027,233Absorption rotor, rotor element, method of manufacturing absorption rotor, and method of manufacturing rotor element20218,260,031'Pattern inspection apparatus, pattern inspection method, and computer-readable recording medium storing a program'20128,233,698'Pattern inspection apparatus, corrected image generation method, and computer-readable recording medium storing program'20128,013,361'Semiconductor device and method for fabricating the same'20117,809,181'Pattern inspection apparatus, image alignment method, displacement amount estimation method, and computer-readable recording medium with program recorded thereon'20107,792,663'Circuit simulation method'20107,709,900'Semiconductor device'20107,655,904'Target workpiece inspection apparatus, image alignment method, and computer-readable recording medium with program recorded thereon'20107,577,288'Sample inspection apparatus, image alignment method, and program-recorded readable recording medium'20097,562,327'Mask layout design improvement in gate width direction'20097,551,767'Pattern inspection apparatus'20097,519,593'Data searching system, method of synchronizing metadata and data searching apparatus'20097,476,957'Semiconductor integrated circuit'20097,421,109'Pattern inspection apparatus'20087,415,149'Pattern inspection apparatus'20087,279,727'Semiconductor device'20077,230,435'Capacitance measurement circuit'20077,209,584'Pattern inspection apparatus'20077,171,640'System and method for operation verification of semiconductor integrated circuit'20077,126,174'Semiconductor device and method of manufacturing the same'20067,032,208'Defect inspection apparatus'20066,982,555'Semiconductor device'20066,967,409'Semiconductor device and method of manufacturing the same'20056,894,520'Semiconductor device and capacitance measurement method'20056,883,160'Pattern inspection apparatus'20056,876,208'Semiconductor device and method of checking semiconductor storage device'20056,847,119'Semiconductor device and method of manufacturing the same'20056,709,950'Semiconductor device and method of manufacturing the same'20046,594,598'Method for controlling production line'20036,492,672'Semiconductor device'20026,396,943'Defect inspection method and defect inspection apparatus'20026,281,562'Semiconductor device which reduces the minimum distance requirements between active areas'20016,205,570'Method for designing LSI circuit pattern'20016,124,160'Semiconductor device and method for manufacturing the same'20006,084,716'Optical substrate inspection apparatus'20005,879,983'Semiconductor device and method for manufacturing the same'19995,856,754'Semiconductor integrated circuit with parallel/serial/parallel conversion'19995,844,809'Method and apparatus for generating two-dimensional circuit pattern'19985,841,173'MOS semiconductor device with excellent drain current'19985,675,168'Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device'19975,610,430'Semiconductor device having reduced gate overlapping capacitance'19975,404,410'Method and system for generating a bit pattern'19955,185,812'Optical pattern inspection system'19935,100,234'Method and apparatus for aligning two objects, and method and apparatus for providing a desired gap between two objects'19924,988,197'Method and apparatus for aligning two objects, and method and apparatus for providing a desired gap between two objects'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2012Patents assigned to TOSHIBA KK (16)· patent assignee history
1991–2009Based in Yokohama, JP· patent location history
1997–2007Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (17)· patent assignee history
1997–2010Based in Osaka, JP· patent location history
2001–2011Based in Kyoto, JP· patent location history
2002–2012Based in Kanagawa, JP· patent location history
2005–2006Patents assigned to RENESAS TECH CORP (3)· patent assignee history
2009–2011Patents assigned to PANASONIC CORP (5)· patent assignee history
2009–2010Patents assigned to ADVANCED MASK INSPECTION TECH (3)· patent assignee history
2021Based in Kakogawa, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MATSUSHITA ELECTRIC INDUSTRIAL CO LTD171997–2007
TOSHIBA KK161991–2012
PANASONIC CORP52009–2011
ADVANCED MASK INSPECTION TECH32009–2010
RENESAS TECH CORP32005–2006
Locations
LocationPatentsSpan
Osaka, JP131997–2010
Kyoto, JP122001–2011
Yokohama, JP121991–2009
Kanagawa, JP62002–2012
Kakogawa, JP12021