An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

Claims

81 · 8 independent · depth 6

81 granted claims

›1.independentA semiconductor device comprising:nan isolation for surrounding an active region of a substrate; an interconnection formed on the isolation; an insula…+32

›2.↳ 1The semiconductor device of claim 1, wherein the isolation is a trench isolation.d2+14

›3.↳ 2The semiconductor device of claim 2, wherein the trench isolation has a top surface at a higher level than a surface of the active region.d3+1

›5.↳ 2The semiconductor device of claim 2, wherein a top surface of the trench isolation provided under the interconnection is at a higher level than a surf…d3+11

›9.↳ 5The semiconductor device of claim 5, wherein the conductive layer has at least a tungsten plug.d4+6

›13.↳ 5The semiconductor device of claim 5, further comprising a sidewall made of an insulating material formed on a side of the interconnection.d4

›16.↳ 5The semiconductor device of claim 5, wherein an underlying film having high etching selectivity in a dry etching process against the insulating film i…d4

›19.↳ 5The semiconductor device of claim 5, further comprising,na gate insulating film formed on the active region, a gate electrode formed on the gate insul…d4+1

›6.↳ 1The semiconductor device of claim 1, wherein the conductive layer has at least a tungsten plug.d2+2

›12.↳ 1The semiconductor device of claim 1, further comprising a sidewall made of an insulating material formed on a side of the interconnection.d2

›15.↳ 1The semiconductor device of claim 1, wherein an underlying film having high etching selectivity in a dry etching process against the insulting film is…d2

›18.↳ 1The semiconductor device claim 1, further comprising,na gate insulating film formed on the active region, a gate electrode formed on the gate insulati…d2+1

›24.↳ 1The semiconductor device of claim 1, wherein a silicon nitride film is entirely formed under the insulating film.d2

›28.↳ 1The semiconductor device of claim 1 further comprising,na gate insulating film formed on the active region, and a gate electrode formed on the gate in…d2+2

›39.↳ 1The semiconductor device of claim 1, wherein the insulating film is formed directly on the top surface of the interconnection.d2

›40.↳ 1The semiconductor device of claim 1, wherein the active region and the interconnection are directly connected to the conductive layer.d2

›44.↳ 1The semiconductor device of claim 1, wherein the conductive layer is formed only in the hole.d2

›47.↳ 1The semiconductor device of claim 1, wherein the conductive layer is a plug.d2

›51.↳ 1The semiconductor device of claim 1, further comprising sidewalls made of an insulating material formed on both sides of the interconnection.d2

›55.↳ 1The semiconductor device of claim 1, wherein the interconnection member is directly connected to the conductive layer.d2

›25.independentA semiconductor device comprising:nan isolation for surrounding an active region of a substrate; an interconnection formed on the isolation; an insula…+14

›29.↳ 25The semiconductor device of claim 25, further comprising,na gate insulating film formed on the active region, and a gate electrode formed on the gate …d2+3

›36.↳ 25The semiconductor device of claim 25, wherein the interconnection is formed directly on the isolation.d2

›41.↳ 25The semiconductor device of claim 25, wherein the active region and the interconnection are directly connected to the conductive layer.d2

›48.↳ 25The semiconductor device of claim 25, wherein the conductive layer is a plug.d2

›52.↳ 25The semiconductor device of claim 25, wherein sidewalls made of an insulating material are formed on both sides of the interconnection.d2

›56.↳ 25The semiconductor device of claim 25, wherein the interconnection member is directly connected to the conductive layer.d2

›66.↳ 25The semiconductor device of claim 25, wherein the isolation has a top surface at a higher level than a surface of the active region.d2

›69.↳ 25The semiconductor device of claim 25, wherein the isolation is a trench isolation, andna step portion in a boundary between the active region and the …d2

›72.↳ 25The semiconductor device of claim 25, wherein the isolation is a trench isolation, andna top surface of the trench isolation provided under the interc…d2+1

›78.↳ 25The semiconductor device of claim 25, wherein the conductive layer is formed only in the hole.d2

›26.independentA semiconductor device comprising:nan isolation for surrounding an active region of a substrate; an interconnection formed on the isolation; an insula…+13

›33.↳ 26The semiconductor device of claim 26, wherein the gate electrode and the interconnection have at least a polysilicon film.d2

›37.↳ 26The semiconductor device of claim 26, wherein the interconnection is formed directly on the isolation.d2

›42.↳ 26The semiconductor device of claim 26, wherein the active region and the interconnection are directly connected to the conductive layer.d2

›45.↳ 26The semiconductor device of claim 26, further comprising a sidewall made of an insulating material formed on a side of the interconnection.d2

›49.↳ 26The semiconductor device of claim 26, wherein the conductive layer is a plug.d2

›53.↳ 26The semiconductor device of claim 26, further comprising sidewalls made of an insulating material formed on both sides of the interconnection.d2

›57.↳ 26The semiconductor device of claim 26, wherein the interconnection member is directly connected to the conductive layer.d2

›59.↳ 26The semiconductor of claim 26, wherein the interconnection and gate electrode are formed m the same process step.d2

›67.↳ 26The semiconductor device of claim 26, wherein the isolation has a top surface at a higher level than a surface of the active region.d2

›70.↳ 26The semiconductor device of claim 26, wherein the isolation is a trench isolation, andna step portion in a boundary between the active region and the …d2

›73.↳ 26The semiconductor device of claim 26, wherein the isolation is a trench isolation, andna top surface of the trench isolation provided under the interc…d2

›76.↳ 26The semiconductor device of claim 26, further comprising:na source/drain region formed in the active region provided on both sides of the gate electro…d2

›79.↳ 26The semiconductor device of claim 26, wherein the conductive layer is formed only in the hole.d2

›27.independentA semiconductor device comprising:nan isolation for surrounding an active region of a substrate; an interconnection formed on the isolation and not on…+14

›30.↳ 27The semiconductor device of claim 27, further comprising,na gate insulating film formed on the active region, and a gate electrode formed on the gate …d2+3

›38.↳ 27The semiconductor device of claim 27, wherein the interconnection is formed directly on the isolation.d2

›43.↳ 27The semiconductor device of claim 27, wherein the active region and the interconnection are directly connected to the conductive layer.d2

›46.↳ 27The semiconductor device of claim 27, further comprising a sidewall made of an insulating material formed on a side of the interconnection.d2

›50.↳ 27The semiconductor device of claim 27, wherein the conductive layer is a plug.d2

›54.↳ 27The semiconductor device of claim 27, further comprising sidewalls made of an insulating material formed on both sides of the interconnection.d2

›58.↳ 27The semiconductor device of claim 27, wherein the interconnection member is directly connected to the conductive layer.d2

›68.↳ 27The semiconductor device of claim 27, wherein the isolation has a top surface at a higher level than a surface of the active region.d2

›71.↳ 27The semiconductor device of claim 27, wherein the isolation is a trench isolation, andna step portion in a boundary between the active region and the …d2

›74.↳ 27The semiconductor device of claim 27, wherein the isolation is a trench isolation, andna top surface of the trench isolation provided under the interc…d2

›80.↳ 27The semiconductor device of claim 27, wherein the conductive layer is formed only in the hole.d2

›35.independentThe semiconductor device of 1, wherein the interconnection is formed directly on the isolation.

›63.independentA semiconductor device comprising:nan isolation for surrounding an active region of a substrate; an interconnection formed on the isolation; an insula…

›64.independentA semiconductor device comprising:nan isolation for surrounding an active region of a substrate; an interconnection formed on the isolation; an insula…

›65.independentA semiconductor device comprising:nan isolation for surrounding an active region of a substrate; an interconnection formed on the isolation; an insula…

Classifications

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USPC · US Patent Classification

257/774

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Type	Document	Date
related publication	US 20030205820 A1	6 Nov 2003

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