Inventor
Varughese Mathew
Inventor
Austin, TX, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1044%
H01LSemiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10DInorganic electric semiconductor devices6%
C23CCoating metallic material5%
H05KPrinted circuits3%
B08BCleaning in general2%
C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients2%
C08LCompositions of macromolecular compounds2%
C23FNon-mechanical removal of metallic material from surface2%
PatentTitleYear
10,325,876Surface finish for wirebonding201910,217,713Semiconductor device attached to an exposed pad201910,199,339Semiconductor structure with sacrificial anode and method for forming201910,147,697Bond pad structure for semiconductor device packaging20189,978,614Structure and method to minimize warpage of packaged semiconductor devices20189,640,466'Packaged semiconductor device with a lead frame and method for forming'20179,508,632'Apparatus and methods for stackable packaging'20169,431,313'Integrated circuit carrier coating'20169,426,884'System and method for lead frame package degating'20169,412,709'Semiconductor structure with sacrificial anode and passivation layer and method for forming'20169,117,756'Encapsulant with corrosion inhibitor'20159,093,383'Encapsulant for a semiconductor device'20159,012,263'Method for treating a bond pad of a package substrate'20158,955,388'Mold compound compatibility test system and methods thereof'20158,853,867'Encapsulant for a semiconductor device'20148,836,110'Heat spreader for use within a packaged semiconductor device'20148,643,197'Encapsulant for a semiconductor device'20148,586,474'Method to form a via'20138,394,713'Method of improving adhesion of bond pad over pad metallization with a neighboring passivation layer by depositing a palladium layer'20138,168,468'Method of making a semiconductor device including a bridgeable material'20128,003,517'Method for forming interconnects for 3-D applications'20117,993,971'Forming a 3-D semiconductor die structure with an intermetallic formation'20117,932,175'Method to form a via'20117,807,572'Micropad formation for a semiconductor'20107,717,060'Controlled electroless plating'20107,572,723'Micropad for bonding and a method therefor'20097,422,979'Method of forming a semiconductor device having a diffusion barrier stack and structure thereof'20087,410,544'Method for cleaning electroless process tank'20087,378,339'Barrier for use in 3-D integration of circuits'20087,238,601'Semiconductor device having conductive spacers in sidewall regions and method for forming'20077,176,133'Controlled electroless plating'20076,924,232'Semiconductor process and composition for forming a barrier material overlying copper'20056,803,323'Method of forming a component overlying a semiconductor substrate'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2019Patents assigned to FREESCALE SEMICONDUCTOR INC (29)· patent assignee history
2004–2019Based in Austin, TX, US· patent location history
2012–2019Patents assigned to MATHEW VARUGHESE (10)· patent assignee history
2014–2016Patents assigned to CHOPIN SHEILA F (4)· patent assignee history
2015–2019Patents assigned to HIGGINS III LEO M (3)· patent assignee history
2017–2019Patents assigned to NXP USA INC (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 29 | 2004–2019 |
| MATHEW VARUGHESEself | 10 | 2012–2019 |
| NXP USA INC | 6 | 2017–2019 |
| CHOPIN SHEILA F | 4 | 2014–2016 |
| HIGGINS III LEO M | 3 | 2015–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 33 | 2004–2019 |