Inventor
Szu-Po Huang
Inventor
Taichung, TW
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H10HInorganic light-emitting semiconductor devices having potential barriers4%
Y10TTechnical subjects covered by former us classification4%
B22FWorking metallic powder1%
B23PMetal-working not otherwise provided for1%
C01GCompounds containing metals not covered by subclasses c01d or c01f1%
C01PIndexing scheme relating to structural and physical aspects of solid inorganic compounds1%
C09DCoating compositions, e.g. paints, varnishes or lacquers1%
PatentTitleYear
11,056,796Directly flat-attached switching component for active frequency selective surface and fabricating method thereof202110,629,510Package with embedded heat dissipation features202010,629,545Semiconductor device202010,461,0093DIC packaging with hot spot thermal management features201910,446,5203D semiconductor package interposer with die cavity201910,332,823Packaged semiconductor devices201910,157,8133DIC packaging with hot spot thermal management features201810,157,818Methods of cooling packaged semiconductor devices201810,062,665Semiconductor packages with thermal management features for reduced thermal crosstalk20189,985,0013DIC package and methods of forming the same20189,978,660Package with embedded heat dissipation features20189,941,2513DIC packages with heat dissipation structures20189,780,072'3D semiconductor package interposer with die cavity'20179,735,082'3DIC packaging with hot spot thermal management features'20179,595,506'Packages with thermal management features for reduced thermal crosstalk and methods of forming same'20179,583,415'Packages with thermal interface material on the sidewalls of stacked dies'20179,576,938'3DIC packages with heat dissipation structures'20179,496,249'3DIC package and methods of forming the same'20169,385,095'3D semiconductor package interposer with die cavity'20169,379,036'3DIC packages with heat dissipation structures'20169,269,694'Packages with thermal management features for reduced thermal crosstalk and methods of forming same'20169,224,673'Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices'20159,184,128'3DIC package and methods of forming the same'20159,082,743'3DIC packages with heat dissipation structures'20159,076,754'3DIC packages with heat sinks attached to heat dissipating rings'20158,946,887'3DIC packages with heat dissipation structures'20158,911,821'Method for forming nanometer scale dot-shaped materials'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014Patents assigned to CHIOU KUO-CHAN (1)· patent assignee history
2014Patents assigned to HUANG SZU-PO (1)· patent assignee history
2014Patents assigned to IND TECH RES INST (1)· patent assignee history
2014Based in Taipei, TW· patent location history
2015–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (7)· patent assignee history
2015–2020Based in Taichung, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (17)· patent assignee history
2016Based in Hsinchu, TW· patent location history
2021Based in Taoyuan County, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 17 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 7 | 2015–2016 |
| CHIOU KUO-CHAN | 1 | 2014 |
| HUANG SZU-POself | 1 | 2014 |
| IND TECH RES INST | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taichung, TW | 24 | 2015–2020 |
| Taoyuan County, TW | 1 | 2021 |
| Hsinchu, TW | 1 | 2016 |
| Taipei, TW | 1 | 2014 |