Inventor

Ted R. White

Inventor

Austin, TX, US

Overview

44→

Patents

1990–2015

Patent span

Electricity

Primary field (CPC H)

Patents· 44 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices48%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%

H10BElectronic memory devices5%

B82YSpecific uses or applications of nanostructures2%

C23CCoating metallic material1%

C30BSingle-crystal growth1%

H01LSemiconductor devices1%

PatentTitleYear

9,111,908'Split-gate non-volatile memory cells having improved overlap tolerance'2015 8,426,310'Method of forming a shared contact in a semiconductor device'2013 8,390,026'Electronic device including a heterojunction region'2013 8,163,615'Split-gate non-volatile memory cell having improved overlap tolerance and method therefor'2012 8,125,032'Modified hybrid orientation technology'2012 7,927,956'Method for making a semiconductor structure using silicon germanium'2011 7,923,769'Split gate non-volatile memory cell with improved endurance and method therefor'2011 7,923,328'Split gate non-volatile memory cell with improved endurance and method therefor'2011 7,821,067'Electronic devices including a semiconductor layer'2010 7,811,382'Method for forming a semiconductor structure having a strained silicon layer'2010 7,803,670'Twisted dual-substrate orientation (DSO) substrates'2010 7,799,644'Transistor with asymmetry for data storage circuitry'2010 7,781,840'Semiconductor device structure'2010 7,749,829'Step height reduction between SOI and EPI for DSO and BOS integration'2010 7,737,496'Electronic devices including a semiconductor layer'2010 7,700,420'Integrated circuit with different channel materials for P and N channel transistors and method therefor'2010 7,556,992'Method for forming vertical structures in a semiconductor device'2009 7,544,548'Trench liner for DSO integration'2009 7,524,707'Modified hybrid orientation technology'2009 7,494,856'Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor'2009 7,479,422'Semiconductor device with stressors and method therefor'2009 7,402,477'Method of making a multiple crystal orientation semiconductor device'2008 7,288,458'SOI active layer with different surface orientation'2007 7,285,452'Method to selectively form regions having differing properties and structure'2007 7,282,402'Method of making a dual strained channel semiconductor device'2007 7,265,004'Electronic devices including a semiconductor layer and a process for forming the same'2007 7,241,647'Graded semiconductor layer'2007 7,226,833'Semiconductor device structure and method therefor'2007 7,226,820'Transistor fabrication using double etch/refill process'2007 7,208,357'Template layer formation'2007 7,205,210'Semiconductor structure having strained semiconductor and method therefor'2007 7,163,903'Method for making a semiconductor structure using silicon germanium'2007 7,160,769'Channel orientation to enhance transistor performance'2007 7,074,664'Dual metal gate electrode semiconductor fabrication process and structure thereof'2006 7,067,868'Double gate device having a heterojunction source/drain and strained channel'2006 7,056,778'Semiconductor layer formation'2006 7,037,795'Low RC product transistors in SOI semiconductor process'2006 7,029,980'Method of manufacturing SOI template layer'2006 7,018,901'Method for forming a semiconductor device having a strained channel and a heterojunction source/drain'2006 6,838,322'Method for forming a double-gated semiconductor device'2005 6,831,350'Semiconductor structure with different lattice constant materials and method for forming the same'2004 5,918,147'Process for forming a semiconductor device with an antireflective layer'1999 5,589,423'Process for fabricating a non-silicided region in an integrated circuit'1996 4,902,533'Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–1999Patents assigned to MOTOROLA INC (3)· patent assignee history

1990–2015Based in Austin, TX, US· patent location history

2004–2015Patents assigned to FREESCALE SEMICONDUCTOR INC (39)· patent assignee history

2006Based in Crolles, FR· patent location history

2007–2015Patents assigned to WHITE TED R (6)· patent assignee history

2012–2015Patents assigned to WINSTEAD BRIAN A (3)· patent assignee history

2012–2013Patents assigned to ADETUTU OLUBUNMI O (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FREESCALE SEMICONDUCTOR INC	39	2004–2015
WHITE TED Rself	6	2007–2015
MOTOROLA INC	3	1990–1999
WINSTEAD BRIAN A	3	2012–2015
ADETUTU OLUBUNMI O	2	2012–2013

Locations

Location	Patents	Span
Austin, Texas, US	43	1990–2015
Crolles, FR	1	2006