Inventor

Eliezer Weissmann

Inventor

Haifa, IL

Overview

2008–2021

Patent span

Physics

Primary field (CPC G)

Patents· 130 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing48%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use33%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications11%

H04LTransmission of digital information, e.g. telegraphic communication6%

G11CStatic stores1%

G01VGeophysics0%

G09GArrangements or circuits for control of indicating devices using static means to present variable information0%

PatentTitleYear

11,093,278Modifying processor frequency based on interrupt rate2021 11,074,191Linear to physical address translation with support for page attributes2021 11,029,744System, apparatus and method for controlling a processor based on effective stress information2021 10,990,395System and method for communication using a register management array circuit2021 10,990,161Processor having accelerated user responsiveness in constrained environment2021 10,990,155System, apparatus and method for loose lock-step redundancy power management2021 10,990,154System, apparatus and method for loose lock-step redundancy power management2021 10,963,034System, apparatus and method for loose lock-step redundancy power management in a processor2021 10,955,899System, apparatus and method for responsive autonomous hardware performance state control of a processor2021 10,884,483Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency2021 10,705,588Enabling a non-core domain to control memory bandwidth in a processor2020 10,678,319Multi-level loops for computer processor control2020 10,620,682System, apparatus and method for processor-external override of hardware performance state control of a processor2020 10,613,614Dynamically controlling cache size to maximize energy efficiency2020 10,564,699Dynamically controlling cache size to maximize energy efficiency2020 10,558,490Mechanism for issuing requests to an accelerator from multiple threads2020 10,545,793Thread scheduling using processing engine information2020 10,503,550Dynamic performance biasing in a processor2019 10,503,509System and method for communication using a register management array circuit2019 10,503,517Method for booting a heterogeneous system and presenting a symmetric core view2019 10,474,218Dynamically controlling cache size to maximize energy efficiency2019 10,474,216Method and apparatus for providing power state information using in-band signaling2019 10,467,012Apparatus and method for accelerating operations in a processor which uses shared virtual memory2019 10,429,919System, apparatus and method for loose lock-step redundancy power management2019 10,379,596Providing an interface for demotion control information in a processor2019 10,379,904Controlling a performance state of a processor using a combination of package and thread hint information2019 10,372,197User level control of power management policies2019 10,372,198Controlling performance states of processing engines of a processor2019 10,346,195Apparatus and method for invocation of a multi threaded accelerator2019 10,345,889Forcing a processor into a low power state2019 10,324,519Controlling forced idle state operation in a processor2019 10,281,975Processor having accelerated user responsiveness in constrained environment2019 10,275,260Collaborative processor and system performance and power management2019 10,248,181Enabling a non-core domain to control memory bandwidth in a processor2019 10,216,246Multi-level loops for computer processor control2019 10,191,742Mechanism for saving and retrieving micro-architecture context2019 10,185,566Migrating tasks between asymmetric computing elements of a multi-core processor2019 10,175,740Mapping a performance request to an operating frequency in a processor2019 10,162,687Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets2018 10,127,039Extension of CPU context-state management for micro-architecture state2018 10,120,691Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator2018 10,114,448Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency2018 10,095,521Apparatus and method for low-latency invocation of accelerators2018 10,089,113Apparatus and method for low-latency invocation of accelerators2018 10,083,037Apparatus and method for low-latency invocation of accelerators2018 10,078,519Apparatus and method for accelerating operations in a processor which uses shared virtual memory2018 10,067,553Dynamically controlling cache size to maximize energy efficiency2018 10,037,067Enabling a non-core domain to control memory bandwidth in a processor2018 10,007,321Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power2018 10,007,528Computing platform interface with memory management2018 9,983,644Dynamically updating at least one power management operational parameter pertaining to a turbo mode of a processor for increased performance2018 9,971,688Apparatus and method for accelerating operations in a processor which uses shared virtual memory2018 9,939,879Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor2018 9,864,667'Techniques for flexible and dynamic frequency-related telemetry'2018 9,829,957Performance scalability prediction2017 9,811,355'Method and apparatus for selecting an interconnect frequency in a computing system'2017 9,760,160'Controlling performance states of processing engines of a processor'2017 9,760,158'Forcing a processor into a low power state'2017 9,747,221'Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform'2017 9,727,345'Method for booting a heterogeneous system and presenting a symmetric core view'2017 9,720,730'Providing an asymmetric multicore processor system transparently to an operating system'2017 9,710,043'Controlling a guaranteed frequency of a processor'2017 9,684,541'Method and apparatus for determining thread execution parallelism'2017 9,671,853'Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency'2017 9,652,018'Adjusting power consumption of a processing element based on types of workloads to be executed'2017 9,639,372'Apparatus and method for heterogeneous processors mapping to virtual cores'2017 9,618,997'Controlling a turbo mode frequency of a processor'2017 9,600,058'Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power'2017 9,535,487'User level control of power management policies'2017 9,535,838'Atomic operations in PCI express'2017 9,471,490'Dynamically controlling cache size to maximize energy efficiency'2016 9,454,379'Collaborative processor and system performance and power management'2016 9,448,829'Hetergeneous processor apparatus and method'2016 9,442,739'Collaborative processor and system performance and power management'2016 9,442,855'Transaction layer packet formatting'2016 9,405,701'Apparatus and method for accelerating operations in a processor which uses shared virtual memory'2016 9,396,020'Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled accelerator'2016 9,361,116'Apparatus and method for low-latency invocation of accelerators'2016 9,361,101'Extension of CPU context-state management for micro-architecture state'2016 9,354,692'Enabling a non-core domain to control memory bandwidth in a processor'2016 9,348,594'Core switching acceleration in asymmetric multiprocessor system'2016 9,348,401'Mapping a performance request to an operating frequency in a processor'2016 9,329,900'Hetergeneous processor apparatus and method'2016 9,292,068'Controlling a turbo mode frequency of a processor'2016 9,268,378'Techniques and system for managing platform temperature'2016 9,176,565'Controlling operating frequency of a core domain based on operating condition of a non-core domain of a multi-domain processor'2015 9,170,624'User level control of power management policies'2015 9,164,917'Linear to physical address translation with support for page attributes'2015 9,164,923'Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform'2015 9,164,916'Linear to physical address translation with support for page attributes'2015 9,158,693'Dynamically controlling cache size to maximize energy efficiency'2015 9,158,703'Linear to physical address translation with support for page attributes'2015 9,152,205'Mechanism for facilitating faster suspend/resume operations in computing systems'2015 9,152,572'Translation lookaside buffer for multiple context compute engine'2015 9,110,735'Managing performance policies based on workload scalability'2015 9,098,261'User level control of power management policies'2015 9,098,415'PCI express transaction descriptor'2015 9,092,210'Controlling current transients in a processor'2015 9,081,557'Dynamically allocating a power budget over multiple domains of a processor'2015 9,075,610'Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation'2015 9,063,729'Device, system and method of generating an execution instruction based on a memory-access instruction'2015 9,058,201'Managing and tracking thread access to operating system extended features using map-tables containing location references and thread identifiers'2015 9,053,022'Synchronous software interface for an accelerated compute engine'2015 9,032,103'Transaction re-ordering'2015 9,026,829'Package level power state optimization'2015 9,026,682'Prefectching in PCI express'2015 8,996,895'Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates'2015 8,874,947'Method and apparatus of power management of processor'2014 8,806,068'Transaction re-ordering'2014 8,799,620'Linear to physical address translation with support for page attributes'2014 8,799,687'Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates'2014 8,793,404'Atomic operations'2014 8,775,833'Dynamically allocating a power budget over multiple domains of a processor'2014 8,769,316'Dynamically allocating a power budget over multiple domains of a processor'2014 8,726,048'Power management coordination in multi-core processors'2014 8,555,101'PCI express enhancements and extensions'2013 8,549,183'PCI express enhancements and extensions'2013 8,473,642'PCI express enhancements and extensions including device window caching'2013 8,458,498'Method and apparatus of power management of processor'2013 8,447,888'PCI express enhancements and extensions'2013 8,281,083'Device, system and method of generating an execution instruction based on a memory-access instruction'2012 8,230,119'PCI express enhancements and extensions'2012 8,230,120'PCI express enhancements and extensions'2012 8,099,523'PCI express enhancements and extensions including transactions having prefetch parameters'2012 8,073,981'PCI express enhancements and extensions'2011 7,966,511'Power management coordination in multi-core processors'2011 7,930,566'PCI express enhancements and extensions'2011 7,899,943'PCI express enhancements and extensions'2011 7,752,030'Virtualization as emulation support'2010 7,451,333'Coordinating idle state transitions in multi-core processors'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2021Patents assigned to INTEL CORP (129)· patent assignee history

2008–2021Based in Haifa, IL· patent location history

2011–2020Patents assigned to WEISSMANN ELIEZER (38)· patent assignee history

2011–2014Based in Hafia, IL· patent location history

2012–2019Patents assigned to NAVEH ALON (16)· patent assignee history

2013–2019Patents assigned to ROTEM EFRAIM (15)· patent assignee history

2015–2020Patents assigned to GINZBURG BORIS (12)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	129	2008–2021
WEISSMANN ELIEZERself	38	2011–2020
NAVEH ALON	16	2012–2019
ROTEM EFRAIM	15	2013–2019
GINZBURG BORIS	12	2015–2020

Locations

Location	Patents	Span
Haifa, IL	128	2008–2021
Hafia, IL	2	2011–2014