Inventor
Atsuo Koshizuka
Inventor
Tokyo, JP
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores92%
G06FElectric digital data processing3%
H03KPulse technique3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
10,311,939Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system201910,147,478Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system201810,049,722Apparatuses and methods for a memory device with dual common data I/O lines20189,805,786'Apparatuses and methods for a memory device with dual common data I/O lines'20179,576,640'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20179,466,354'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20169,214,205'System with controller and memory'20159,208,852'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20159,082,482'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20159,001,597'Memory system, semiconductor memory device, and wiring substrate, the semiconductor memory device including termination resistance circuit or control circuit'20158,867,252'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20148,842,457'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20148,811,052'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20148,811,053'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20148,811,054'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20148,804,442'Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device'20148,711,595'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission method'20148,644,107'System with controller and memory'20148,614,907'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20138,605,475'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20138,605,474'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20138,605,473'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20138,599,624'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20138,593,893'Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device'20138,582,337'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20138,576,652'Semiconductor memory device, memory system including memory controller, and refresh control method for a semiconductor memory device'20138,531,860'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20138,391,090'Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device'20138,379,479'System with controller and memory'20138,274,850'Memory system, semiconductor memory device, and wiring substrate'20128,213,258'System with controller and memory'20128,199,546'Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system'20128,054,700'Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device'20117,965,581'System with controller and memory'20117,697,369'System with controller and memory'20106,009,038'Addressing unit'19995,852,585'Addressing unit'19985,305,258'Semiconductor memory and memory cell'19945,274,260'Semiconductor device'19935,274,589'Method and apparatus for writing and reading data to/from a memory'19934,882,534'Bipolar-complementary metal oxide semiconductor inverter'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989Based in Kawasaki, JP· patent location history
1993–1998Patents assigned to NIPPON STEEL CORP (4)· patent assignee history
1993–2019Based in Tokyo, JP· patent location history
2010–2014Patents assigned to ELPIDA MEMORY INC (17)· patent assignee history
2012–2015Patents assigned to KOSHIZUKA ATSUO (12)· patent assignee history
2014–2016Patents assigned to PS4 LUXCO SARL (11)· patent assignee history
2017Based in Saitama, JP· patent location history
2018–2019Patents assigned to LONGITUDE LICENSING LTD (2)· patent assignee history
2018Based in Fujimino, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ELPIDA MEMORY INC | 17 | 2010–2014 |
| KOSHIZUKA ATSUOself | 12 | 2012–2015 |
| PS4 LUXCO SARL | 11 | 2014–2016 |
| NIPPON STEEL CORP | 4 | 1993–1998 |
| LONGITUDE LICENSING LTD | 2 | 2018–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 38 | 1993–2019 |
| Fujimino, JP | 1 | 2018 |
| Saitama, JP | 1 | 2017 |
| Kawasaki, JP | 1 | 1989 |