Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

A semiconductor memory device, comprising:na system clock terminal provided to receive a system clock with a first frequency or a second frequency;a data terminal provided to transfer a data therethrough in synchronization with the system clock;a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough;a command terminal provided to receive a command that communicates the data with an outside thereof; andan address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.

A semiconductor memory device, comprising:na first external terminal configured to receive a system clock with a first frequency or a second frequency;a second external terminal configured to receive a read command in synchronization with the system clock;a third external terminal configured to output a data strobe signal in response to the read command, the data strobe signal including a preamble and a toggle transition following to the preamble;a fourth external terminal configured to output a read data in synchronization with the toggle transition of the data strobe signal;a fifth external terminal configured to receive a preamble length information; anda control circuit configured to control a length of the preamble of the data strobe signal based on the preamble length information, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.

A semiconductor memory device, comprising:na first external terminal provided to receive a system clock with a frequency;a second external terminal provided to transfer a data therethrough in synchronization with the system clock;a third external terminal provided to receive a command for communicating the data with an outside thereof;a control circuit configured to produce a data strobe signal, which includes a preamble and a toggle transition following to the preamble, so that the transferring the data is conducted by the toggle transition of the data strobe signal; anda fourth external terminal provided to be supplied an information specifying a length of the preamble of the strobe signal from an outside of the semiconductor memory device, the length of the preamble being changed based on the frequency of the system clock, the length being defined by a number of clock of the system clock.