Inventor

Mustafa N. Kaynak

Inventor
San Diego, CA, US

Overview

50→
Patents
2009–2021
Patent span
Physics
Primary field (CPC G)

Patents· 50 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing35%
G11CStatic stores31%
H03MCoding28%
G11BInformation storage based on relative movement between record carrier and transducer5%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
11,068,186Providing recovered data to a new memory cell at a memory sub-system based on an unsuccessful error correction operation202110,998,923Stopping criteria for layered iterative error correction202110,903,860Error correction code (ECC) operations in memory for providing redundant error correction202110,891,191Apparatuses and methods for generating probabilistic information with current integration sensing202110,872,009Mitigating a voltage condition of a memory cell in a memory sub-system202010,860,416Tiered error correction code (ECC) operations in memory202010,811,090Memory cell state in a valley between adjacent data states202010,732,890Adjusting a parameter for a programming operation based on the temperature of a memory system202010,693,504Apparatuses and methods for staircase code encoding and decoding for storage devices202010,685,725Performing an operation on a memory cell of a memory system at a frequency based on temperature202010,573,377Determining soft data for fractional digit memory cells202010,572,338Estimating an error rate associated with memory202010,540,228Providing data of a memory system based on an adjustable error rate202010,498,367Progressive effort decoder architecture201910,403,378Performing an operation on a memory cell of a memory system at a frequency based on temperature201910,340,014Monitoring error correction operations performed in memory201910,331,514Tiered error correction code (ECC) operations in memory201910,326,479Apparatuses and methods for layer-by-layer error correction201910,312,944Error correction code (ECC) operations in memory for providing redundant error correction201910,289,484Apparatuses and methods for generating probabilistic information with current integration sensing201910,248,500Apparatuses and methods for generating probabilistic information with current integration sensing201910,193,577Stopping criteria for layered iterative error correction201910,135,465Error correction methods and apparatuses using first and second decoders201810,110,256Apparatuses and methods for staircase code encoding and decoding for storage devices201810,061,643Estimating an error rate associated with memory20189,990,988Determining whether a memory cell state is in a valley between adjacent data states20189,904,594'Monitoring error correction operations performed in memory'20189,875,792Determining soft data for fractional digit memory cells20189,685,243'Determining soft data from a hard read'20179,654,144'Progressive effort decoder architecture'20179,577,673'Error correction methods and apparatuses using first and second decoders'20179,558,064'Estimating an error rate associated with memory'20179,412,472'Determining soft data from a hard read'20169,391,645'Determining soft data using a classification code'20169,355,730'Mapping between program states and data patterns'20169,318,205'Mapping between program states and data patterns'20169,268,629'Dual mapping between program states and data patterns'20169,229,848'Determining soft data for fractional digit memory cells'20169,190,174'Determining soft data from a hard read'20159,116,822'Stopping criteria for layered iterative error correction'20159,081,674'Dual mapping between program states and data patterns'20159,065,483'Determining soft data using a classification code'20159,064,575'Determining whether a memory cell state is in a valley between adjacent data states'20158,996,967'Rendering data write errors detectable'20158,977,808'Mapping between program states and data patterns'20158,788,743'Mapping between program states and data patterns'20148,745,466'Detecting data-write errors'20148,510,642'System and method for map detector for symbol based error correction codes'20138,290,102'Adaptive data dependent noise prediction (ADDNP)'20127,561,640'Method and apparatus for interative noise whitening with causal and anti-causal prediction filters'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009Based in Tempe, AZ, US· patent location history
2012–2015Patents assigned to ST MICROELECTRONICS INC (4)· patent assignee history
2012–2015Patents assigned to PARTHASARATHY SIVAGNANAM (3)· patent assignee history
2012–2021Based in San Diego, CA, US· patent location history
2013–2015Patents assigned to KAYNAK MUSTAFA N (5)· patent assignee history
2014–2021Patents assigned to MICRON TECHNOLOGY INC (43)· patent assignee history
2014–2015Patents assigned to KHAYAT PATRICK R (4)· patent assignee history
2015Based in San Bernardino, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC432014–2021
KAYNAK MUSTAFA Nself52013–2015
KHAYAT PATRICK R42014–2015
ST MICROELECTRONICS INC42012–2015
PARTHASARATHY SIVAGNANAM32012–2015
Locations
LocationPatentsSpan
San Diego, California, US482012–2021
San Bernardino, California, US12015
Tempe, AZ, US12009