LexDanaLexDanabeta
Inventor

Francois Henley

Inventor
Los Gatos, CA, US

Overview

150→
Patents
1986–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 150 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems8%
Y10TTechnical subjects covered by former us classification7%
G01RMeasuring electric variables5%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information4%
H01LSemiconductor devices4%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
PatentTitleYear
11,037,841Light emitting diode (LED) test apparatus and method of manufacture202110,989,755Light emitting diode (LED) test apparatus and method of manufacture202110,978,429Light emitting diode (LED) mass-transfer apparatus and method of manufacture202110,962,586Light emitting diode (LED) test apparatus and method of manufacture202110,683,588Shaped silicon ingot using layer transfer202010,600,697Light emitting diode (LED) test apparatus and method of manufacture202010,186,630Seed wafer for GaN thickening using gas- or liquid-phase epitaxy201910,164,144Bond and release layer transfer process201810,087,551Method and device for slicing a shaped silicon ingot using layer transfer201810,041,187Techniques for forming optoelectronic devices20189,859,458'Bond and release layer transfer process'20189,640,711'Substrate cleaving under controlled stress conditions'20179,460,908'Method and device for slicing a shaped silicon ingot using layer transfer'20169,362,439'Layer transfer of films utilizing controlled shear region'20169,356,181'Substrate cleaving under controlled stress conditions'20169,336,989'Method of cleaving a thin sapphire layer from a bulk material by implanting a plurality of particles and performing a controlled cleaving process'20169,257,339'Techniques for forming optoelectronic devices'20169,159,605'Controlled process and resulting device'20158,993,410'Substrate cleaving under controlled stress conditions'20158,835,282'Controlled process and resulting device'20148,637,382'Layer transfer of films utilizing thermal flux regime for energy controlled cleaving'20148,623,137'Method and device for slicing a shaped silicon ingot using layer transfer'20148,563,402'Method and structure for fabricating solar cells using a thick layer transfer process'20138,329,557'Techniques for forming thin films by implantation with reduced channeling'20128,330,126'Race track configuration and method for wafering silicon solar substrates'20128,293,619'Layer transfer of films utilizing controlled propagation'20128,241,996'Substrate stiffness method and resulting devices for layer transfer process'20128,222,119'Apparatus and method of temperature control during cleaving processes of thick materials'20128,153,513'Method and system for continuous large-area scanning implantation process'20128,143,165'Method for fabricating semiconductor devices using strained silicon bearing material'20128,133,800'Free-standing thickness of single crystal material and method having carrier lifetimes'20128,124,499'Method and structure for thick layer transfer using a linear accelerator'20128,110,480'Method and structure for fabricating solar cells using a thick layer transfer process'20128,071,463'Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process'20118,012,851'Method and structure for fabricating solar cells'20118,012,855'Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process'20118,012,852'Controlled process and resulting device'20117,910,458'Method and structure using selected implant angles using a linear accelerator process for manufacture of free standing films of materials'20117,911,016'Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process'20117,863,157'Method and structure for fabricating solar cells using a layer transfer process'20117,846,818'Controlled process and resulting device'20107,811,900'Method and structure for fabricating solar cells using a thick layer transfer process'20107,781,305'Controlled cleaving process'20107,776,717'Controlled process and resulting device'20107,772,088'Method for manufacturing devices on a multi-layered substrate utilizing a stiffening backing substrate'20107,759,217'Controlled process and resulting device'20107,759,220'Method and structure for fabricating solar cells using a layer transfer process'20107,674,687'Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process'20107,629,666'Method and structure for implanting bonded substrates for electrical conductivity'20097,598,153'Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species'20097,595,499'Method and system for fabricating strained layers for the manufacture of integrated circuits'20097,547,609'Method and structure for implanting bonded substrates for electrical conductivity'20097,479,441'Method and apparatus for flag-less water bonding tool'20097,470,600'Method and device for controlled cleaving process'20087,462,526'Method for fabricating semiconductor devices using strained silicon bearing material'20087,427,554'Manufacturing strained silicon substrates using a backing material'20087,410,887'Controlled process and resulting device'20087,399,680'Method and structure for implanting bonded substrates for electrical conductivity'20087,391,047'System for forming a strained layer of semiconductor material'20087,390,724'Method and system for lattice space engineering'20087,378,330'Cleaving process to fabricate multilayered substrates using low implantation doses'20087,371,660'Controlled cleaving process'20087,354,815'Method for fabricating semiconductor devices using strained silicon bearing material'20087,351,644'Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process'20087,348,258'Method and device for controlled cleaving process'20087,166,520'Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process'20077,160,790'Controlled cleaving process'20077,147,709'Non-contact etch annealing of strained layers'20067,094,666'Method and system for fabricating strained layers for the manufacture of integrated circuits'20067,078,317'Method and system for source switching and in-situ plasma bonding'20067,056,808'Cleaving process to fabricate multilayered substrates using low implantation doses'20066,890,838'Gettering technique for wafers made using a controlled cleaving process'20056,790,747'Method and device for controlled cleaving process'20046,632,724'Controlled cleaving process'20036,582,999'Controlled cleavage process using pressurized fluid'20036,558,802'Silicon-on-silicon hybrid wafer assembly'20036,548,382'Gettering technique for wafers made using a controlled cleaving process'20036,528,391'Controlled cleavage process and device for patterned films'20036,526,997'Dry cleaning method for the manufacture of integrated circuits'20036,511,899'Controlled cleavage process using pressurized fluid'20036,500,268'Dry cleaning method'20026,500,732'Cleaving process to fabricate multilayered substrates using low implantation doses'20026,486,041'Method and device for controlled cleaving process'20026,458,672'Controlled cleavage process and resulting device using beta annealing'20026,458,723'High temperature implant apparatus'2002RE037847'Method and apparatus for testing LCD panel array prior to shorting bar removal'20026,448,152'Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer'20026,413,837'Controlled cleavage process and device for patterned films'20026,391,740'Generic layer transfer methodology by controlled cleavage process'20026,335,264'Controlled cleavage thin film separation process using a reusable substrate'20026,321,134'Clustertool system software using plasma immersion ion implantation'20016,294,814'Cleaved silicon thin film with rough surface'20016,290,804'Controlled cleavage process using patterning'20016,291,326'Pre-semiconductor process implant and post-process film separation'20016,291,313'Method and device for controlled cleaving process'20016,291,314'Controlled cleavage process and device for patterned films using a release layer'20016,284,631'Method and device for controlled cleaving process'20016,265,328'Wafer edge engineering method and device'20016,248,649'Controlled cleavage process and device for patterned films using patterned implants'20016,245,161'Economical silicon-on-silicon hybrid wafer assembly'20016,207,005'Cluster tool apparatus using plasma immersion ion implantation'20016,187,110'Device for patterned films'20016,184,111'Pre-semiconductor process implant and post-process film separation'20016,162,705'Controlled cleavage process and resulting device using beta annealing'20006,159,824'Silicon-on-silicon wafer bonding process using a thin film blister-separation method'20006,159,825'Controlled cleavage thin film separation process using a reusable substrate'20006,155,909'Controlled cleavage system using pressurized fluid'20006,153,524'Cluster tool method using plasma immersion ion implantation'20006,146,979'Pressurized microbubble thin film separation process using a reusable substrate'20006,103,599'Planarizing technique for multilayered substrates'20006,083,324'Gettering technique for silicon-on-insulator wafers'20006,048,411'Silicon-on-silicon hybrid wafer assembly'20006,033,974'Method for controlled cleaving process'20006,013,563'Controlled cleaning process'20006,013,567'Controlled cleavage process using pressurized fluid'20006,010,579'Reusable substrate for thin film separation'20005,994,207'Controlled cleavage process using pressurized fluid'19995,985,742'Controlled cleavage process and device for patterned films'19995,801,824'Large area defect monitor tool for manufacture of clean surfaces'19985,790,247'Technique for determining defect positions in three dimensions in a transparent structure'19985,631,733'Large area defect monitor tool for manufacture of clean surfaces'19975,615,039'Electro-optical element and its manufacturing method'19975,570,011'Method for testing an electronic device using voltage imaging'19965,543,729'Testing apparatus and connector for liquid crystal display substrates'19965,504,438'Testing method for imaging defects in a liquid crystal display substrate'19965,465,052'Method of testing liquid crystal display substrates'19955,459,410'Method and apparatus for automatically inspecting and repairing an active matrix LCD panel'19955,459,409'Testing device for liquid crystal display base plate'19955,444,385'Testing apparatus for liquid crystal display substrates'19955,432,461'Method of testing active matrix liquid crystal display substrates'19955,406,213'Instrument for testing liquid crystal display base plates'19955,391,985'Method and apparatus for measuring high speed logic states using voltage imaging with burst clocking'19955,387,788'Method and apparatus for positioning and biasing an electro-optic modulator of an electro-optic imaging system'19955,363,037'Method and apparatus for testing LCD panel array'19945,285,150'Method and apparatus for testing LCD panel array'19945,235,272'Method and apparatus for automatically inspecting and repairing an active matrix LCD panel'19935,212,374'Method and apparatus for positioning and biasing an electro-optic modulator of an electro-optic imaging system'19935,177,437'High-density optically-addressable circuit board probe panel and method for use'19935,175,504'Method and apparatus for automatically inspecting and repairing a simple matrix circuit panel'19925,170,127'Capacitance imaging system using electro-optics'19925,164,565'Laser-based system for material deposition and removal'19925,157,327'Method and apparatus for electro-optically measuring a voltage signal'19925,124,635'Voltage imaging system using electro-optics'19925,097,201'Voltage imaging system using electro-optics'19925,095,262'Electro-optic sampling system clock and stimulus pattern generator'19925,081,687'Method and apparatus for testing LCD panel array prior to shorting bar removal'19925,073,754'Method and apparatus for testing LCD panel array using a magnetic field sensor'19914,983,911'Voltage imaging system using electro-optics'19914,862,075'High frequency test head using electro-optics'19894,588,950'Test system for VLSI digital circuit and method of testing'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2002Patents assigned to PHOTON DYNAMICS INC (32)· patent assignee history
1989–1992Based in San Jose, CA, US· patent location history
1991–2010Based in Los Gatos, CA, US· patent location history
1999–2020Patents assigned to SILICON GENESIS CORP (106)· patent assignee history
2002–2018Based in Aptos, CA, US· patent location history
2011–2016Patents assigned to HENLEY FRANCOIS J (15)· patent assignee history
2018–2019Patents assigned to QMAT INC (4)· patent assignee history
2018–2021Based in Saratoga, CA, US· patent location history
2018Based in Santa Clara, CA, US· patent location history
2021Patents assigned to APPLE INC (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SILICON GENESIS CORP1061999–2020
PHOTON DYNAMICS INC321989–2002
HENLEY FRANCOIS Jself152011–2016
APPLE INC42021
QMAT INC42018–2019
Locations
LocationPatentsSpan
Los Gatos, California, US731991–2010
Aptos, California, US642002–2018
Saratoga, California, US92018–2021
San Jose, California, US21989–1992
Santa Clara, California, US12018