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Inventor

Norihito Masuda

Inventor
Yokohama, JP

Overview

18→
Patents
2011–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 18 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H01LSemiconductor devices26%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation11%
H05KPrinted circuits9%
Y10TTechnical subjects covered by former us classification9%
B23KSoldering or unsoldering4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H04KSecret communication2%
PatentTitleYear
10,833,044Package-on-package assembly with wire bonds to encapsulation surface202010,593,643Package-on-package assembly with wire bonds to encapsulation surface202010,062,661Package-on-package assembly with wire bonds to encapsulation surface20189,716,075'Semiconductor chip assembly and method for making same'20179,691,731'Package-on-package assembly with wire bonds to encapsulation surface'20179,337,165'Method for manufacturing a fan-out WLP with package'20169,224,717'Package-on-package assembly with wire bonds to encapsulation surface'20159,137,903'Semiconductor chip assembly and method for making same'20159,093,435'Package-on-package assembly with wire bonds to encapsulation surface'20158,969,133'Package-on-package assembly with wire bonds to encapsulation surface'20158,957,520'Microelectronic assembly comprising dielectric structures with different young modulus and having reduced mechanical stresses between the device terminals and external contacts'20158,890,304'Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer material'20148,859,420'Structure and method of making interconnect element, and multilayer wiring board including the interconnect element'20148,786,070'Microelectronic package with stacked microelectronic elements and method for manufacture thereof'20148,618,659'Package-on-package assembly with wire bonds to encapsulation surface'20138,525,338'Chip with sintered connections to package'20138,487,421'Microelectronic package with stacked microelectronic elements and method for manufacture thereof'20137,923,828'Structure and method of making interconnect element, and multilayer wiring board including the interconnect element'2011

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2011–2014Based in Tokyo, JP· patent location history
2013–2020Patents assigned to TESSERA INC (15)· patent assignee history
2013–2015Patents assigned to MASUDA NORIHITO (7)· patent assignee history
2013–2015Patents assigned to HABA BELGACEM (6)· patent assignee history
2013–2015Patents assigned to MOHAMMED ILYAS (6)· patent assignee history
2013–2015Patents assigned to SATO HIROAKI (6)· patent assignee history
2013–2020Based in Yokohama, JP· patent location history
2013–2015Based in Kanagawa, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TESSERA INC152013–2020
MASUDA NORIHITOself72013–2015
HABA BELGACEM62013–2015
MOHAMMED ILYAS62013–2015
SATO HIROAKI62013–2015
Locations
LocationPatentsSpan
Yokohama, JP122013–2020
Kanagawa, JP42013–2015
Tokyo, JP22011–2014