LexDanaLexDanabeta
Inventor

Timothy Thurgate

Inventor
Sunnyvale, CA, US

Overview

60→
Patents
1999–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 60 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices37%
H10BElectronic memory devices25%
G11CStatic stores20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H01LSemiconductor devices5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,644,016Charge-trapping memory device20209,559,216'Semiconductor memory device and method for biasing same'20179,524,971'Techniques for providing a semiconductor memory device'20169,263,133'Techniques for providing a semiconductor memory device'20169,019,759'Techniques for providing a semiconductor memory device'20158,547,738'Techniques for providing a semiconductor memory device'20138,531,878'Techniques for providing a semiconductor memory device'20138,415,734'Memory device protection layer'20138,409,952'Method of forming an electronic device including forming a charge storage element in a trench of a workpiece'20138,208,296'Apparatus and method for extended nitride layer in a flash memory'20128,148,770'Memory device with buried bit line structure'20128,076,712'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'20117,952,938'Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory'20117,888,218'Using thick spacer for bitline implant then remove'20117,785,965'Dual storage node memory devices and methods for fabricating the same'20107,767,517'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'20107,746,705'Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory'20107,696,038'Methods for fabricating flash memory devices'20107,671,405'Deep bitline implant to avoid program disturb'20107,626,869'Multi-phase wordline erasing for flash memory'20097,489,560'Reduction of leakage current and program disturbs in flash memory devices'20097,462,907'Method of increasing erase speed in memory arrays'20087,301,193'Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell'20077,125,763'Silicided buried bitline process for a non-volatile memory cell'20067,067,381'Structure and method to reduce drain induced barrier lowering'20067,049,188'Lateral doped channel'20067,009,271'Memory device with an alternating Vss interconnection'20066,963,106'Memory array with memory cells having reduced short channel effects'20056,911,704'Memory cell array with staggered local inter-connect structure'20056,908,816'Method for forming a dielectric spacer in a non-volatile memory device'20056,773,990'Method for reducing short channel effects in memory cells and related structure'20046,770,938'Diode fabrication for ESD/EOS protection'20046,653,189'Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory'20036,524,914'Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory'20036,518,072'Deposited screen oxide for reducing gate edge lifting'20036,487,121'Method of programming a non-volatile memory cell using a vertical electric field'20026,456,536'Method of programming a non-volatile memory cell using a substrate bias'20026,417,081'Process for reduction of capacitance of a bitline for a non-volatile memory cell'20026,410,956'Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices'20026,387,755'Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting'20026,366,501'Selective erasure of a non-volatile memory cell of a flash memory device'20026,349,062'Selective erasure of a non-volatile memory cell of a flash memory device'20026,337,246'Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing'20026,329,687'Two bit flash cell with two floating gate regions'20016,329,257'Method for laterally peaked source doping profiles for better erase control in flash memory devices'20016,329,273'Solid-source doping for source/drain to eliminate implant damage'20016,268,624'Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing'20016,255,165'Nitride plug to reduce gate edge lifting'20016,236,596'Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices'20016,188,113'High voltage transistor with high gated diode breakdown, low body effect and low leakage'20016,180,468'Very low thermal budget channel implant process for semiconductors'20016,177,322'High voltage transistor with high gated diode breakdown voltage'20016,168,637'Use of a large angle implant and current structure for eliminating a critical mask in flash memory processing'20016,153,487'Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects'20006,147,907'Biasing scheme to reduce stress on non-selected cells during read'20006,143,612'High voltage transistor with high gated diode breakdown, low body effect and low leakage'20006,103,602'Method and system for providing a drain side pocket implant'20006,049,479'Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell'20006,025,240'Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices'20006,005,808'Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2020Based in Sunnyvale, CA, US· patent location history
2000–2006Patents assigned to ADVANCED MICRO DEVICES INC (33)· patent assignee history
2005–2013Patents assigned to SPANSION LLC (18)· patent assignee history
2011–2017Patents assigned to THURGATE TIMOTHY (8)· patent assignee history
2013–2017Patents assigned to MICRON TECHNOLOGY INC (6)· patent assignee history
2013–2017Patents assigned to BANNA SRINIVASA RAO (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED MICRO DEVICES INC332000–2006
SPANSION LLC182005–2013
THURGATE TIMOTHYself82011–2017
MICRON TECHNOLOGY INC62013–2017
BANNA SRINIVASA RAO32013–2017
Locations
LocationPatentsSpan
Sunnyvale, California, US601999–2020