A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

Claims

25 · 3 independent · depth 4

25 granted claims

›1.independentA flash EEPROM memory cell comprising: a substrate; a source region in the substrate at which a source voltage is applied during erasure of the flash …+11

›2.↳ 1The flash EEPROM memory cell of claim 1, wherein: the source voltage is in the range of 0 V to 10 V; the control voltage is in the range of 0 V to -20…d2

›3.↳ 1The flash EEPROM memory cell of claim 1, wherein the difference in the source voltage and the control voltage is sufficiently large to induce electron…d2

›4.↳ 1The flash EEPROM memory cell of claim 1, further comprising: a first well located in the substrate and enclosing the source region and the drain regio…d2+5

›10.↳ 1The flash EEPROM memory cell of claim 1, further comprising a modulator associated with the back biasing connection, wherein the modulator is used to …d2+1

›12.↳ 1The flash EEPROM memory cell of claim 1, wherein the first biasing voltage is greater than 0 volts and less than or equal 0.5 volts during erasure of …d2

›13.independentA method of erasing a flash EEPROM memory cell having a source region, a drain region, a substrate, and a control gate, wherein the method comprising …+7

›14.↳ 13The method of claim 13, further comprising the steps of: enclosing the source region and the drain region in a first well within the substrate, wherei…d2+1

›16.↳ 13The method of claim 13, wherein: the step of applying the source voltage to the source region includes the step of applying the source voltage within …d2

›17.↳ 13The method of claim 13, further comprising the step of applying the source voltage simultaneously or prior to the application of the back biasing volt…d2

›18.↳ 13The method of claim 13, wherein the step of applying the back biasing voltage includes the step of applying the back biasing voltage in a range that i…d2

›19.↳ 13The method of claim 13, further comprising the step of associating a modulator with the back biasing voltage, wherein the modulator is used to modulat…d2+1

›21.independentA method of erasing a flash EEPROM memory cell having a source region, a drain region, a substrate, and a control gate, wherein the method comprising …+4

›22.↳ 21The method of claim 21, wherein the step of applying a back voltage further includes the steps of: connecting a modulator in series with the substrate…d2+1

›24.↳ 21The method of claim 21, further comprising the steps of: enclosing the source region and the drain region in a first well within the substrate; connec…d2+1

Classifications

2 codes

USPC · US Patent Classification

365/185.27365/185.17

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David Nelms

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