Inventor
Viren Khandekar
Inventor
Flower Mound, TX, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1047%
H01LSemiconductor devices33%
H05KPrinted circuits8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
Y02PClimate change mitigation technologies in the production or processing of goods6%
PatentTitleYear
10,804,233Wafer-level chip-scale package device having bump assemblies configured to maintain standoff height202010,304,758Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active wafer201910,032,749Three-dimensional chip-to-wafer integration20189,721,912'Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality'20179,583,425'Solder fatigue arrest for wafer level package'20179,472,451'Technique for wafer-level processing of QFN packages'20169,425,064'Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages'20169,324,687'Wafer-level passive device integration'20169,230,903'Multi-die, high current wafer level package'20169,219,043'Wafer-level package device having high-standoff peripheral solder bumps'20159,190,391'Three-dimensional chip-to-wafer integration'20159,093,333'Integrated circuit device having extended under ball metallization'20159,087,732'Wafer-level package device having solder bump assemblies that include an inner pillar structure'20159,087,779'Multi-die, high current wafer level package'20159,040,408'Techniques for wafer-level processing of QFN packages'20158,860,222'Techniques for wafer-level processing of QFN packages'20148,643,150'Wafer-level package device having solder bump assemblies that include an inner pillar structure'20148,575,493'Integrated circuit device having extended under ball metallization'20138,084,871'Redistribution layer enhancement to improve reliability of wafer level packaging'20117,989,961'Redistribution layer enhancement to improve reliability of wafer level packaging'20117,569,939'Self alignment features for an electronic assembly'20097,482,199'Self alignment features for an electronic assembly'20097,190,078'Interlocking via for package via integrity'20077,135,771'Self alignment features for an electronic assembly'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2009Patents assigned to INTEL CORP (3)· patent assignee history
2006–2009Based in Chandler, AZ, US· patent location history
2011–2020Patents assigned to MAXIM INTEGRATED PRODUCTS (19)· patent assignee history
2011–2020Patents assigned to KHANDEKAR VIREN (5)· patent assignee history
2011–2014Patents assigned to SAMOILOV ARKADII (3)· patent assignee history
2011–2020Based in Flower Mound, TX, US· patent location history
2015–2020Patents assigned to THAMBIDURAI KARTHIK (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MAXIM INTEGRATED PRODUCTS | 19 | 2011–2020 |
| KHANDEKAR VIRENself | 5 | 2011–2020 |
| INTEL CORP | 3 | 2006–2009 |
| SAMOILOV ARKADII | 3 | 2011–2014 |
| THAMBIDURAI KARTHIK | 2 | 2015–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Flower Mound, Texas, US | 20 | 2011–2020 |
| Chandler, AZ, US | 4 | 2006–2009 |